List of Research Topics and Ideas of VLSI for MS and Ph.D. Thesis.

- High-throughput VLSI architecture for soft-decision decoding with ORBGRAND
- Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing
- ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture
- Evaluating the Performances of Memristor, FinFET, and Graphene TFET in VLSI Circuit Design
- VLSI mask optimization: From shallow to deep learning
- Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal
- A Novel High-Performance Hybrid Full Adder for VLSI Circuits
- PGOpt: Multi-objective design space exploration framework for large-Scale on-chip power grid design in VLSI SoC using evolutionary computing technique
- Testing single via related defectsin digital VLSI designs
- An Improved Impulse Noise Removal VLSI Architecture Using DTBDM Method
- VLSI Implementation of Multi-channel ECG Lossless Compression System
- A Scalable VLSI Architecture for Illumination-Invariant Heterogeneous Face Recognition
- Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support
- Compact 3D Thermal Model for VLSI and ULSI Interconnect Network Reliability Verification
- Simultaneous Parametric and Functional Testing of Digital VLSI During Radiation Experiments
- A New 4-2 Compressor for VLSI Circuits and Systems
- An ultra-low-power CNFET-based improved Schmitt trigger design for VLSI sensor applications
- Performance Analysis of Clock Gating Designs in Low Power Vlsi Circuits
- Flexible scheme for reconfiguring 2D mesh-connected VLSI subarrays under row and column rerouting
- A Survey on VLSI Implementation of AES Algorithm with Dynamic S-Box
- High-Throughput VLSI architecture for Soft-Decision decoding with ORBGRAND
- Methods for Ensuring Full Traceability of the Production Testing Results of the Digital VLSI
- Low Power Circuit Design for Footed Quasi Resistance Scheme In 45NM VLSI Technology
- Fast Auto-Correction algorithm for Digital VLSI Circuits
- Review of VLSI Architecture of Cryptography Algorithm for IOT Security
- The VLSI Realization of Sign-Magnitude Decimal Multiplication Efficiency
- Gate-Overlap Tunnel Field-Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications
- VLSI design of a fast one-stage independent component extracting system based on ICA-R algorithm
- Fully Reused VLSI Architectu Encoding for DSRC Applica
- VLSI Architecture for DWT using 5/3 Wavelet Coefficient using Vedic Math’s
- Design and vlsi implementation of a decimation filter for hearing aid applications
- Analysis and Comparison of Leakage Power Reduction Techniques for VLSI Design
- A low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system
- Study and Analysis of Digital Counters for VLSI Applications
- Synthesis of VLSI Structural Cell Partitioning Using Genetic Algorithm
- VLSI Architecture for 8-bit Reversible Arithmetic Logic Unit based on Programmable Gate
- Features of Designing Digital Processing Systems for Radiolocation Systems Based on Microprocessor VLSI Sets
- Multiple-Criteria Decision Analysis Using VLSI Global Routing
- Performance Evaluation of VLSI Implemented WSN Algorithms
- Soft Error Rate Estimation of VLSI Circuits
- Wave pipelined VLSI architecture for a Viterbi decoder using self reset logic with 0.65 nm technology
- Efficient Band Offset Calculation Method for HEVC and Its VLSI Implementation
- 2021 IEEE 39th VLSI Test Symposium (VTS)
- A spike based learning neuron in analog VLSI
- Computing Orientation of an Image by Projection Method and its VLSI Implementation
- A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
- The First Ge Nanosheets GAAFET CMOS Inverters Fabricated by 2D Ge/Si Multilayer Epitaxy, Ge/Si Selective Etching
- Novel Architecture for Lifting Discrete Wavelet Packet Transform With Arbitrary Tree Structure
- Back-Gate Network Extraction Free from Dynamic Self-Heating in FD SOI
- Improvement of Nanotwinned Copper Thermal Stability for High Temperature Heterogeneous Integration
- DFT Models of Ferroelectric Hafnium-Zirconium Oxide Stacks With and Without Dielectric Interlayers
- Selective Area Epitaxy of Axial Wurtzite-InAs Nanowire on InGaAs NW by MOCVD
- Calculation of Field Dependent Mobility in MoS2 and WS2 with Multi-Valley Monte Carlo Method
- Ultra-thin Hf0.5Zr0.5O2 Ferroelectric Tunnel Junction with High Current Density
- Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering
- On-Wafer Electronic Layer Detectors Array (ELDA) for e-beam Imaging in Advanced Lithographic Systems
- Contact engineered charge plasma junctionless transistor for suppressing tunneling leakage
- Quantum Tunneling PUF: A Chip Fingerprint for Hardware Security
- Ferroelectric and Antiferroelectric Hf/Zr oxide films: past, present and future
- An Approach to Diminish the Leakage Power in Complementary MOS VLSI Circuits
- Benchmarking the Performance of Heterogeneous Stacked RRAM with CFETSRAM and MRAM for Deep Neural Network Application Amidst Variation and Noise
- Multi-bit cryogenic flash memory on Si/SiGe and Ge/GeSi heterostructures
- Tensor-Centric Processor Architecture for Applications in Advanced Driver Assistance Systems
- Evaluation de la complexit d’implantation en VLSI par la synth se architecturale: une exp rience en filtrage adaptatif
- A precise debugging method and defect diagnosis with mass big-data analysis in the designed high-dense array for rapid yield improvement in a logic platform
- Dynamic Mapping Mechanism to Compute DNN Models on a Resource-limited NoC Platform
- Bandgap-Engineered Tunneling Layer on Operation Characteristics of Poly-Ge Charge-Trapping Flash Memory Devices
- Reconfigurable Database Processor for Query Acceleration on FPGA
- Holistic and In-Context Design Flow for 2.5 D Chiplet-Package Interaction Co-Optimization
- ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design
- Quantum dot celluar automata-based encoder and priority encoder circuits: Low latency and area efficient design
- Shutdown mode implementation for Boost and Inverting Buck-Boost converter
- AN ELEGANCE OF A NOVEL DIGITAL FILTER USING MAJORITY LOGIC FOR SNR IMPROVEMENT IN SIGNAL PROCESSING
- Recent Progress on Flexible Capacitive Pressure Sensors: From Design and Materials to Applications
- Prototypage d’algorithmes adaptatifs par un outil de synthèse d’architectures VLSI.
- ALGORITMOS PARA PROBLEMAS DE STEINER COM APLICAÇÕES EM PROJETO DE CIRCUITOS VLSI
- An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM
- Prospective incorporation of booster in carbon interconnects for high-speed integrated circuits
- Laser beam testing of finished integrated circuits
- A survey of in-spin transfer torque mram computing
- Oxytocin modulates neural processing of mitral/tufted cells in the olfactory bulb
- Power Efficient Bit Lines: A Succinct Study
- Introduction: Soft Error Modeling
- Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation
- Adiabatic Logic-Based Area-and Energy-Efficient Full Adder Design
- Improved Noise Margin and Reduced Power Consumption in Subthreshold Adiabatic Logic Using Dual Rail Power Supply
- IMPROVING SIZE-BOUNDS FOR SUBCASES OF SQUARE-SHAPED SWITCHBOX ROUTING
- Design and Performance Evaluation of Highly Efficient Adders in Nanometer Technology
- Qualitative and quantitative analysis of parallel-prefix adders
- 4-Bit Ripple Carry Adder Using Area-Efficient Full Adder in CMOS Technology
- Systolic-Architecture-Based Matrix Multiplications and Its Realization for Multi-Sensor Bias Estimation Algorithms
- BiPart: a parallel and deterministic hypergraph partitioner
- Dealing with Aging and Yield in Scaled Technologies
- Ultraefficient imprecise multipliers based on innovative 4: 2 approximate compressors
- A Low Power Approach for Designing 12-Bit Current Steering DAC
- Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization
- Gain-Cell Embedded DRAM Under Cryogenic Operation–A First Study
- Communication and performance evaluation of 3-ary n-cubes onto network-on-chips
- A New Function Mapping Approach in Defective Nanocrossbar Array Using Unique Number Sequence
- Design, Simulation and Comparative Analysis of Performance Parameters of a 4-bit CMOS based Full Adder Circuit using Microwind and DSch at Various …
- A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems
- Leakage-Tolerant Low-Power Wide Fan-in OR Logic Domino Circuit
- Carver Mead:” It’s All About Thinking,” A Personal Account Leading up to the First Microwave Transistor
- Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller
- An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder
- Advanced Silicon & Semiconducting Silicon-Alloy Based Materials & Devices
- A Novel Modeling-Attack Resilient Arbiter-PUF Design
- Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links
- Parallel algorithms
- Transistor self-heating: The rising challenge for semiconductor testing
- Adaptive Forward Body Bias Voltage Generator
- PVT Aware Analysis of ISCAS C17 Benchmark Circuit
- Hard-to-Detect Fault Analysis in FinFET SRAMs
- Design and comparative analysis of on-chip sigma delta ADC for signal processing applications
- Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs
- Passivity-based non-fragile control of a class of uncertain fractional-order nonlinear systems
- Impact of Spacers in Raised Source/Drain 14 nm Technology Node InGaAs-nFinFET on Short Channel Effects
- High Speed Energy Efficient Multiplier Using 20nm FinFET Technology
- Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits
- Design and Analysis of 10T SRAM Cell with Stability Characterizations
- Evaluation of Real-Time Embedded Systems in HILS and Delay Issues
- Implementation and Analysis of Low Power Consumption Full Swing GDI Full Adders
- A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory
- [HTML][HTML] X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution
- A New Improved V-Square-Controlled Buck Converter With Rail-to-Rail OTA-Based Current-Sensing Circuits
- A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n-and p-type Flip-Flops
- Variability Analysis of On-Chip Interconnect System Using Prospective Neural Network
- Low Power NAND Gate–based Half and Full Adder/Subtractor Using CMOS Technique
- Synchronization of mutual coupled fractional order one-sided lipschitz systems
- Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders
- Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme
- High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register
- High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone
- Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique
- Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator
- Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V
- Machine-learning-based self-tunable design of approximate computing
- A novel current-controlled memristor-based chaotic circuit
- Performance Analysis of MoS2FET for Electronic and Spintronic Application
- Asynchronous Four-Phase and Two-Phase Circuits: Testing and Design for Testability
- Controlling GIDL Using Core–Shell Technique in Conventional Nano-Wire
- New FDNR and FDNC Simulation Configurations Using Inverted VDDIBAs
- Optimal Mappings of the Spectrum of BPSK/QPSK Sequences to Finite Polynomial Fields and Rings
- Impact of Multi-Metal Gate Stacks on the Performance of ß-Ga2O3 MOS Structure
- On the Reliability of In-Memory Computing: Impact of Temperature on Ferroelectric TCAM
- Design of Prominent Single-Precision 32-Bit Floating-Point Adder Using Single-Electron Transistor Operating at Room Temperature
- HIPER: Low Power, High Performance and Area-Efficient Hardware Accelerators for Hidden Periodicity Detection using Ramanujan Filter Banks
- A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation
- Design of a new BUS for low power reversible computation
- Controlling Mode Transition Noise Occurred at Ground Rail in Data Preserving MTCMOS Shift Register
- Diversity Schemes in Multi-hop Visible Light Communications for 6G Networks
- Fabrication of Micro-Compliant Mechanisms Using Micro-Stereolithography
- A 27S/32S DC-balanced line coding scheme for PAM-4 signaling
- Game Theory-based Parameter-Tuning for Path Planning of UAVs
- A Low Latency Stochastic Square Root Circuit
- New Resistorless FDNR Simulation Configuration Employing CDDITAs
- An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0 V
- Improved Store-Carry-Forward Scheme for Information Dissemination in Unfavorable Vehicular Distribution
- Effect of surface modification treatment on top-pinned MTJ with perpendicular easy axis
- Design and Implementation of an Efficient Mixed Parallel-Pipeline SAD Architecture for HEVC Motion Estimation
- Negative Voltage Generator and Current DAC Based Regulator For Flash Memory
- A non-autonomous chaotic system with no equilibrium
- SIXOR: Single-Cycle In-Memristor XOR
- Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
- Towards energy-efficient STT-MRAM design with multi-modes reconfiguration
- HT-IWT-DCT-Based Hybrid Technique of Robust Image Watermarking
- GPU-Accelerated Soft Error Rate Analysis of Large-Scale Integrated Circuits
- Performance Evaluation of Sub 5 nm GAA NWMBCFET using Silicon Carbide Source/Drain Material
- A novel ultra-low power 7T full adder design using mixed logic
- Reversible Fade Gate as Decoder, Encoder and Full Adder
- A novel parallel prefix adder for optimized Radix-2 FFT processor
- Smart Soldier Health Monitoring System Incorporating Embedded Electronics
- Theoretical Analysis of Defected Ground Multiband Rectangular Shape Microstrip Patch Antenna
- Design of Efficient Ternary Subtractor
- Novel CDDITA-Based-Grounded Inductance Simulation Circuits
- Trim Time Reduction in Analog/RF ICs Based on Inter-Trim Correlation
- Ferroelectric HfO2 Memory Transistors with High-? Interfacial Layer and Write Endurance Exceeding 1010 Cycles
- Design and Analysis of Low-Power SRAM
- High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic
- Selective Flip-Flop Optimization for Circuit Reliability
- Effect of Developer Temperature on Photoresist Contrast in Grayscale Lithography
- Power Series Representation Op logical Functions and its Applications to Error Detection and Error Correction Codes.(Dept. E)
- Creating Fastest Self timing Reference Path for High Speed Memory Designs
- Blockchain-enabled traceable, transparent transportation system for blood bank
- Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System
- Enhancement of ovonic threshold switching characteristics using nanometer-scale virtual electrode formed within ultrathin hafnium dioxide interlayer
- Neural networks integrated circuit with switchable gait pattern for insect-type microrobot
- Analog and Radio-Frequency Performance of Hetero-Gate-Dielectric FD SOI MOSFET in Re-S/D Technology
- Stumped nature hyperjerk system with fractional order and exponential nonlinearity: Analog simulation, bifurcation analysis and cryptographic applications
- Field-free and sub-ns magnetization switching of magnetic tunnel junctions by combining spin-transfer torque and spin–orbit torque
- Fundamentals of microelectronics
- Comparative Analysis of Channel Estimation Techniques in Vehicular Communication
- Statistical analysis of vehicle detection in the ITS application for monitoring the traffic and road accident using internet of things
- 3-D CMOS chip stacking for security ICs featuring backside buried metal power delivery networks with distributed capacitance
- Sensor Localization in WSNs Using Rotating Directional-Antenna at the Base Station
- A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications
- FPGA implementation of fast digital FIR and IIR filters
- Uniform 4-Stacked Ge0.9Sn0.1 Nanosheets Using Double Ge0.95Sn0.05 Caps by Highly Selective Isotropic Dry Etch
- A 3–7 GHz CMOS Power Amplifier Design for Ultra-Wide-Band Applications
- Fault-tolerant hamiltonian cycles and paths embedding into locally exchanged twisted cubes
- Error-Controlling Technique in Wireless Communication
- Human Action Recognition Using a New Hybrid Descriptor
- Minimization of Peak-to-Average Power Ratio in DHT Precoded OFDM System by A-Law Companding
- Machine Learning Oriented Dynamic Cost Factors-Based Routing in Communication Networks
- Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning
- Physical synthesis for advanced neural network processors
- A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition
- On the Best-Partition Communication Complexity
- IMPLEMENTATION OF DIVISION AND SQUARE ROOT: MODELING AND EVALUATIONS
- Structural and Optical Analysis of Bulk-Hetero Interface Between MoS2: Pentacene
- Realization of a Low Profile, Wideband Omni-directional Antenna for Ku-band Airborne Applications
- Ultracompact channel add-drop filter based on single multimode nanobeam photonic crystal cavity
- Structural and Optical Characterization of EZO Thin Film for Application in Optical Waveguide
- Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm
- A Survey of Semantic Segmentation on Biomedical Images Using Deep Learning
- PAPR Reduction in OFDM for VLC System
- A Survey on Proactive and Reactive Channel Switching Techniques in Cognitive Radios
- FPGA-based Hardware Acceleration for SVM Machine Learning Algorithm
- Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy
- A Multichannel Link-Layer Cooperation Protocol (MLCP) for Cognitive Radio Ad Hoc Network
- AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction
- Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling
- A PVT aware differential delay circuit and its performance variation due to power supply noise
- A Survey on Methodologies and Database Used for Facial Emotion Recognition
- A Survey Study of Diseases Diagnosed Through Imaging Methodology Using Ultrasonography
- Special Session: Physical Attacks through the Chip Backside: Threats, Challenges, and Opportunities
- MOS based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance for biomedical applications: Analysis and proof of concept
- Automated Simulator for the Validation of Bio-Impedance Devices
- The Architectural Optimizations of a Low-Complexity and Low-Latency FFT Processor for MIMO-OFDM Communication Systems
- An Optimal Design of 16 Bit ALU
- Analysis of Power Adaptation Techniques Over Beaulieu-Xie Fading Model
- Design and Analysis of Wearable Step-Shaped Sierpinski Fractal Antenna for WBAN Applications
- ASSURE: RTL Locking Against an Untrusted Foundry
- Design of Dynamic Induction Charging Vehicle for Glimpse of Future: Cutting Down the Need for High-Capacity Batteries and Charging Stations
- Performance Analysis of Speck Cipher Using Different Adder Architectures
- A Comparative Analysis of Statistical Model and Spectral Subtractive Speech Enhancement Algorithms
- Dimensionality Reduction Using Principal Component Analysis for Lecture Attendance Management System
- Design and implementation of current mode circuit for digital modulation
- SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator
- A Compact IPD Based on-Chip Bandpass Filter for 5G Radio Applications
- An automated parallel simulation flow for cyber-physical system design
- Conformal Omni Directional Antenna for GPS Applications
- Recognition of Natural and Computer-Generated Images Using Convolutional Neural Network
- SPIDER-based out-of-order execution scheme for Ht-MPSOC
- Fast Encoding Using X-Search Pattern and Coded Block Flag Fast Method
- Design and Simulation of a Dual-Band Radiometer for Humidity and Temperature Profiling
- Voice Controlled IoT Based Grass Cutter Powered by Solar Energy
- Periodic Octagon Split Ring Slot Defected Ground Structure for MIMO Microstrip Antenna
- COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing
- Design of Electronic Instrumentation for Isotope Processing
- Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution
- Design and analysis of improved high-speed adaptive filter architectures for ECG signal denoising
- Compact and efficient structure of 8-bit S-box for lightweight cryptography
- Virtually Doped Silicon-on-Insulator Junctionless Transistor for Reduced OFF-State Leakage Current
- Reliability-Driven Voltage Optimization for NCFET-based SRAM Memory Banks
- [HTML][HTML] Design and simulation of high-performance 2: 1 multiplexer based on side-contacted FED
- Special Session–Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits
- Enhancement of magnetic coupling and magnetic anisotropy in MTJs with multiple CoFeB/MgO interfaces for high thermal stability
- Nonlinear Circuits and Systems with Memristors: Nonlinear Dynamics and Analogue Computing via the Flux-Charge Analysis Method
- The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising
- Information Theory-Based Defense Mechanism Against DDOS Attacks for WSAN
- TxSim: Modeling training of deep neural networks on resistive crossbar systems
- Automated Observability Analysis for Mixed-Signal Circuits
- Silicon-on-nothing electrostatically doped junctionless tunnel field effect transistor (son-ed-jltfet): A short channel effect resilient design
- Fault Detection and Classification in Microgrid Using Wavelet Transform and Artificial Neural Network
- [HTML][HTML] Development of neural networks chip generating driving waveform for electrostatic motor
- Computer Laboratory
- Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing
- Recent Development in Analytical Model for Graphene Field Effect Transistors for RF Circuit Applications
- Phenomenological CNN model of a somatosensory effects
- Reusability and Scalability of an SoC Testbench in Mixed-Signal Verification—The Inevitable Necessity
- Power-and area-optimized high-level synthesis implementation of a digital down converter for software-defined radio applications
- 3–21 GHz broadband and high linearity distributed low noise amplifier
- 64-GHz datapath demonstration for bit-parallel SFQ microprocessors based on a gate-level-pipeline structure
- Resynthesize Technique for Soft Error-Tolerant Design of Combinational Circuits
- FPGA implementations for data encryption and decryption via concurrent and parallel computation: A review
- Vertically integrated computing labs using open-source hardware generators and cloud-hosted FPGAs
- Fast shared-memory streaming multilevel graph partitioning
- Comparison of NMOS and PMOS Input Driving Dynamic Comparator in 45nm Technology
- Hybrid Forecasting Model Based on Nonlinear Auto-Regressive Exogenous Network, Fourier Transform, Self-organizing Map and Pattern Recognition Model for Hour …
- Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency
- Design of Low Power Barrel Shifter Architecture by Using Proposed MUX Based CORDIC in CMOS Logic
- Adaptive filtering algorithms in acoustic echo cancellation: a case study in architecure complexity evaluation
- Performance improvement of elliptic curve cryptography system using low power, high speed 16× 16 Vedic multiplier based on reversible logic
- Density Gradient Study on Junctionless Stack Nano-Sheet with Stack Gate Oxide for Low Power Application
- All-digital built-in self-test scheme for charge-pump phase-locked loops
- FPGA Hardware Acceleration of Soft Error Rate Estimation of Digital Circuits
- Power-aware hold optimization for ASIC physical synthesis
- Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits
- New LMI Criterion to the Robust Stability of Discrete-Time Systems with Time-Varying Delays and Generalized Overflow Nonlinearities
- A dual-mode successive approximation register analog to digital converter to detect malicious off-chip power noise measurement attacks
- FPGA Design of SAR Type ADC Based Analog Input Module for Industrial Applications
- Secure energy efficient network priority routing protocol for effective data collection and key management in dynamic WSNs
- A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture
- Monolithic 3D stacked multiply-accumulate units
- Guidance-based improved depth upsampling with better initial estimate
- Circuit and system-level aspects of phase change memory
- An Active, Low-Power, 10Gbps, Current-based Transimpedance Amplifier in a Broadband Optical Receiver Front-End
- Conception de deux points mémoire statiques CMOS durcis contre l’effet des aléas logiques provoqués par l’environnement radiatif spatial
- Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits. Electronics 2021, 10 …
- A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices
- Design and Fabrication of a Polymer Microring Resonator: Polymer Microring Resonator
- Design for Testability of Low Dropout Regulators
- Magnonic band structure in CoFeB/Ta/NiFe meander-shaped magnetic bilayers
- Novel Circuit Model of Multi-walled CNT Bundle Interconnects Using Multi-valued Ternary Logic
- Higher-order Network Analysis Takes Off, Fueled by Classical Ideas and New Data
- High-Level Synthesis of Custom DSP Blocks using Distributed Arithmetic
- Enhancement-Mode Atomic-Layer-Deposited In2O3 Transistors With Maximum Drain Current of 2.2 A/mm at Drain Voltage of 0.7 V by Low-Temperature Annealing …
- An Active, Low-Power, 10Gbps, Current-based Transimpedance Amplifier in a Broadband Optical Receiver Front-End
- Design of High-Speed Binary Counter Architecture for Low-Power Applications
- A Systematic Review on an Embedded Web Server Architecture
- Build-in compact and efficient temperature sensor array on field programmable gate array
- SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level
- Low power, high-performance reversible logic enabled CNTFET SRAM cell with improved stability
- Design and Verification of Advanced Microcontroller Bus Architecture-Advanced Peripheral Bus (AMBA-APB) Protocol
- A Reconfigurable Architecture to Implement Linear Transforms of Image Processing Applications
- Etude du bruit électrique en 1/f et des fluctuations RTS aux basses fréquences dans le transistor MOS submicronique
- sonal communication, June 16, 1994.
- In-memory realization of SHA-2 using ReVAMP architecture
- Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range Query Over NVRAM
- Design and validation of an artificial neural network based on analog circuits
- Insight into threshold voltage and drain induced barrier lowering in negative capacitance field effect transistor
- The past and future of multi-gate field-effect transistors: Process challenges and reliability issues
- A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS……………….. K. Shiba …
- [HTML][HTML] A Survey on Application Specific Processor Architectures for Digital Hearing Aids
- A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era
- Multilevel Hypergraph Partitioning with Vertex Weights Revisited
- [HTML][HTML] The involution tool for accurate digital timing and power analysis
- Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency. Electronics 2021, 10, 71
- Memristor based high speed and low power consumption memory design using deep search method
- Comparative Analysis of Adder for Various CMOS Technologies
- Design of Parallel Sorting System Using Discrete-Time Neural Circuit Model
- Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits
- Process Variation-Aware Soft Error Rate Estimation Method for Integrated Circuits
- Global placement with deep learning-enabled explicit routability optimization
- Microcomputer Application in Motion Control
- Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip
- Capacitance-to-Digital Converter for Operation under Uncertain Harvested Voltage down to 0.3 V with No Trimming, Reference and Voltage Regulation
- Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications
- A Theoretical Study of Design Rewiring Using ATPG
- FPGA Implementation of Bio-inspired Computing Based Deep Learning Model
- Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators
- Employing the Empirical Mode Decomposition to Denoise the Random Telegraph Noise
- Dependence of metal gate work function variation for various ferroelectric thickness on electrical parameters in NC-FinFET
- [HTML][HTML] A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs
- Electronically tunable third-order dual-mode quadrature sinusoidal oscillators employing VDCCs and all grounded components
- FPGA Implementation of Radix-4-Based Two-Dimensional FFT with and Without Pipelining Using Efficient Data Reordering Scheme
- TRENDS IN DISTRIBUTED OBJECT COM-PUTING
- Designing a New 4: 2 compressor using an efficient multi-layer full-adder based on nanoscale quantum-Dot cellular automata
- Introduction to Dual Mode Logic (DML)
- 3-D IC: An Overview of Technologies, Design Methodology, and Test Strategies
- A Novel Plaintext-Related Color Image Encryption Scheme Based on Cellular Neural Network and Chen’s Chaotic System
- Spatial Coverage of FM Radio Signal Variation Measurement and Comparison of two Major Radio Stations within Akwa Ibom State
- Fabrication and selective wet etching of Si0. 2Ge0. 8/Ge multilayer for Si0. 2Ge0. 8 channel gate-all-around MOSFETs
- High-performance area-efficient polynomial ring processor for CRYSTALS-Kyber on FPGAs
- Dynamic workload allocation for edge computing
- Non-volatile memory behavior of interfacial InOx layer in InAs nano-wire field-effect transistor for neuromorphic application
- A Case Study on FPGA Implementation of Parts Counting Orientation Recognition Method for Industrial Vision System
- A Survey of FIR Filter Design Techniques: Low-complexity, Narrow Transition-band and Variable Bandwidth
- A low-power dynamic ternary full adder using carbon nanotube field-effect transistors
- Design and analysis of (5, 10) regular LDPC encoder using MRP technique
- Low-Voltage DML
- Efficient Ternary Compressor Design Using Capacitive Threshold Logic in CNTFET Technology
- Realization of 8 x 4 Barrel shifter with 4-bit binary to Gray converter using FinFET for Low Power Digital Applications
- Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm
- High-speed programmable photonic circuits in a cryogenically compatible, visible-NIR 200 mm CMOS architecture
- S ntese de Alto N vel de Protocolos para a Abordagem IP sobre ATM
- A Systematic Review of Approximate Adders: Accuracy and Performance Analysis
- Evaluation of low power consumption network on chip routing architecture
- Tiny robots and sensors need tiny batteries—here’s how to do it
- Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation
- Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications
- Gradual magnetization switching via domain nucleation driven by spin–orbit torque
- TEM studies during development of a 4-megabit DRAM
- Circuit Design Using Genetic Programming: An Illustrative Study
- Machine Learning for Electronic Design Automation: A Survey
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- Suppression of ambipolar behavior and simultaneous improvement in RF performance of gate-overlap tunnel field effect transistor (GOTFET) devices
- Analysis on High-Performance Full Adders
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- On the role of system software in energy management of neuromorphic computing
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- Impact of the SiO2 interface layer on the crystallographic texture of ferroelectric hafnium oxide
- Voltage-gate assisted spin-orbit torque magnetic random access memory for high-density and low-power embedded application
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- Design of AES-Based Encryption Chip for IoT Security
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- Amorphous InGaZnO Thin-Film Transistors With Sub-10-nm Channel Thickness and Ultrascaled Channel Length
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- Design of Soft-Error-Aware SRAM With Multi-Node Upset Recovery for Aerospace Applications
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- Design and FPGA Synthesis of an Efficient Synchronous Counter with Clock-Gating Techniques
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- Experimental Examination of Component-Differentially-Challenged XOR PUF Circuits
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- Low Powered Self-Testable ALU
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- Approximate Array Multipliers
- 2 Eduction
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- ObfusX: routing obfuscation with explanatory analysis of a machine learning attack
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- Hardware Verification: Theory and Practice
- Decomposition Methods of FSM Implementation
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- Review on performance analysis of P3HT: PCBM-based bulk heterojunction organic solar cells
- Silico-Algorithmes et Arithm etique des Ordinateurs
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- On the Design of a Fault-Tolerant Scalable Three Dimensional NoC-Based Digital Neuromorphic System With On-Chip Learning
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- Process validation test of CNTFET using Stanford model
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- Spin–orbit torque and Dzyaloshinskii–Moriya interaction in perpendicularly magnetized heterostructures with iridium
- On the Origin of Wake-Up and Antiferroelectric-Like Behavior in Ferroelectric Hafnium Oxide
- Website Development for Trading Between Farmers and Government
- Modeling and experimental analysis of an internally-cooled vapor chamber
- Logic Synthesis of Sequential Logic Circuits for Adiabatic Quantum-Flux-Parametron Logic
- Further stability analysis of neutral-type Cohen-Grossberg neural networks with multiple delays
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- Verilog Implementation of Biometric-Based Transmission of Fused Images Using Data Encryption Standards Algorithm
- Learned smartphone isp on mobile npus with deep learning, mobile ai 2021 challenge: Report
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- Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node
- Enhancing Security and Trust of IoT Devices–Internet of Secured Things (IoST)
- Dual Metal Double Gate Ge-Pocket TFET (DMG-DG-Ge-Pocket TFET) with Hetero Dielectric: DC & Analog Performance Projections
- DML Energy-Delay Tradeoffs and Optimization
- Analysis and Design of On-Chip RF Interconnect Line for Wideband True-Time Delay Line Application
- RECON: Resource-efficient CORDIC-based neuron architecture
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- Toward novel designs of reversible ternary 6: 2 Compressor using efficient reversible ternary full-adders
- 3D-aCortex: An ultra-compact energy-efficient neurocomputing platform based on commercial 3D-NAND flash memories
- Study and Implementation of Ladder Logic Conversion to VHDL for Field Programmable Gate Array (FPGA)-Based Programmable Logic Controllers (PLC)
- Enhanced Lubrication Ability of Polyalphaolefin and Polypropylene Glycol by COOH-Functionalized Multiwalled Carbon Nanotubes as an Additive
- A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes
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- Mobility enhancement techniques for Ge and GeSn MOSFETs
- Towards the development of backing layer for piezoelectric micromachined ultrasound transducers
- EN SYNTHESE D’ARCHITECTURE
- Implementation of Autoencoders with Systolic Arrays through OpenCL
- Ultra-high-performance magnetic nonvolatile level converter flip-flop with spin-hall assistance for dual-supply systems with power gating architecture
- Adaptive Deconvolution-based stereo matching Net for Local Stereo Matching
- Investigation of thick GaAs: Cr pixel sensors for X-ray imaging applications
- Damage in silicon after reactive ion etching
- Unraveling the optical contrast in Sb2Te and AgInSbTe phase-change materials
- Emerging technologies and the security of western Europe
- An overview of biological applications and fundamentals of new inlet and vacuum ionization technologies
- Realization of a self-powered ZnSnO MSM UV photodetector that uses surface state controlled photovoltaic effect
- Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles
- Lowering the Schottky Barrier Height by Titanium Contact for High-Drain Current in Mono-layer MoS 2 Transistor
- Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application
- On the crossing numbers of join products of W_ {4}+ P_ {n} and W_ {4}+ C_ {n}
- A Crystal-Less BLE Transmitter With Clock Recovery From GFSK-Modulated BLE Packets
- Visibilidade em Poligonos utilizando algoritmos paralelos
- Um Protocolo SR ARQ Ponto-a-Multiponto com Reconhecimento Acumulativo para Comunica cões a Altas Velocidades
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- Phase Change Random Access Memory for Neuro-Inspired Computing
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- Study on Power Minimization techniques in SAR ADC Devices by Using Comparators Circuits
- Built-In Self-Test (BIST) Methods for MEMS: A Review
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- Terrestrial precise positioning system using carrier phase from burst signals and optically distributed time and frequency reference
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- A fractional-order CNN hyperchaotic system for image encryption algorithm
- Genfloor: Interactive generative space layout system via encoded tree graphs
- Our Perspectives
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- High-speed CMOS-compatible III-V on Si membrane photodetectors
- Configurable DSI partitioned approximate multiplier
- Stacking faults and precipitates in annealed and co-sputtered C49 TiSi2 films
- Trading-o Power versus Area through a Parameterizable Model for Virtual Memory Manage
- Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency
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- A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS
- Influence of High-Pressure Annealing Conditions on Ferroelectric and Interfacial Properties of Zr-Rich Hf?Zr1??O2Capacitors
- Fault-based Built-in Self-test and Evaluation of Phase Locked Loops
- Field-programmable gate arrays in a low power vision system
- On undirected two-commodity integral flow, disjoint paths and strict terminal connection problems
- Scheduling Conditional Nested Loops in a Resource Constrained ASIC Design
- Reliability-Aware Multipath Routing of Time-Triggered Traffic in Time-Sensitive Networks
- Time-domain computing in memory using spintronics for energy-efficient convolutional neural network
- End-to-End Data Architecture Considerations for IoT
- Covering problem on fuzzy graphs and its application in disaster management system
- A Time-Frequency Measurement and Evaluation Approach for Body Channel Characteristics in Galvanic Coupling Intrabody Communication
- Crosstalk minimization in network on chip (NoC) links with dual binary weighted code CODEC
- A physical model for bulk gate insulator trap generation during bias-temperature stress in differently processed p-channel FETs
- On the capabilities of Cellular Automata-based MapReduce model in Industry 4.0
- Rail-to-rail dynamic voltage comparator scalable down to pw-range power and 0.15-v supply
- In situ microsectioning and imaging of semiconductor devices using a scanning ion microscope
- Estimation Probabiliste des Ressources, pour la synth ese d’Architectures
- Improved design debugging architecture using low power serial communication protocols for signal processing applications
- An enhanced cost-aware mapping algorithm based on improved shuffled frog leaping in network on chips
- Single Event Transient (SET) Mitigation Circuits With Immune Leaf Nodes
- A Period-Aware Routing Method for IEEE 802.1 Qbv TSN Networks
- Special session: Reliability analysis for ML/AI hardware
- The Japanese fifth generation computing project: curricular applications
- Proposal for ultrafast all-optical pseudo random binary sequence generator using microring resonator-based switches
- Hardware/Software Codesign for Energy Efficiency and Robustness: From Error-Tolerant Computing to Approximate Computing
- TAAL: tampering attack on any key-based logic locked circuits
- Hardware Trojan Prevention and Detection by Filling Unused Space Using Shift registers, Gate-chain and Extra Routing.
- Quiet 2-Level Adiabatic Logic
- Towards a DML Library Characterization and Design with Standard Flow
- Sedenionic formulation for the field equations of multifluid plasma
- Design and analysis of double-gate junctionless vertical TFET for gas sensing applications
- Shared-Memory n-level Hypergraph Partitioning
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- Fast multipole method for 3-D Laplace equation in layered media
- Dielectric spectroscopy and electrical conductivity measurements of a series of orthoconic antiferroelectric liquid crystalline esters
- The unified modeling language reference manual
- Design of a 2–30 GHz Low-Noise Amplifier: A Review
- Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics
- Early Detection of Prediabetes and T2DM Using Wearable Sensors and Internet-of-Things-Based Monitoring Applications
- Road surface detection and differentiation considering surface damages
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- Computer simulation of X-ray topographs of curved silicon crystals
- The analog/RF performance of a strained-Si graded-channel dual-material double-gate MOSFET with interface charges
- Detecting Signature of Virus Using Metamaterial-Based One-Dimensional Multi-layer Photonic Crystal Structure Under Polarized Incidence
- A DTMOS-based power efficient recycling folded cascode operational transconductance amplifier
- Block coordinate descent based algorithm for computational complexity reduction in multichannel active noise control system
- RRAM-Based Neuromorphic Computing Systems
- analysis and Simulation of Schottky tunneling using Schottky barrier FET with 2-D analytical modeling
- Investigation of Multiple-valued Logic Technologies for Beyond-binary Era
- Structure and substructure connectivity of alternating group graphs
- Power and area efficient stochastic artificial neural networks using spin–orbit torque-based true random number generator
- Improvised hierarchy of Floating Point Multiplication using 5: 3 Compressor
- Research on digital image watermark encryption based on hyperchaos
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- 6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency
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- BiCoSS: toward large-scale cognition brain with multigranular neuromorphic architecture
- Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide.
- TAN modelling of HH-shape microstrip interconnect tree
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- A 189×600 Back-Illuminated Stacked SPAD Direct Time-of-Flight Depth Sensor for Automotive LiDAR Systems
- A Fully Integrated 2.7 µW-70.2 dBm-Sensitivity Wake-Up Receiver with Charge-Domain Analog Front-End,-16.5 dB-SIR, FEC and Cryptographic Checksum
- Learning complexity of simulated annealing
- General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework
- High Current Density in Monolayer MoS2 Doped by AlOx
- A general semantics for logics of affirmation and negation
- Symmetric-Mapping LUT-Based Method and Architecture for Computing XY-Like Functions
- Modelling and Design of 5T, 6T and 7T SRAM Cell Using Deep Submicron CMOS Technology
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- Design of CMOS 6T and 8T SRAM for Memory Applications
- Brain-inspired golden chip free hardware trojan detection
- S ntese L ogica do Protocolo IPv6: Resultado de uma Metodologia visando o Projeto de Protocolos em Hardware
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- A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7 TOPS/W for Tiny AI Edge Devices
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- Binary precision neural network manycore accelerator
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