VLSI Research Topics Ideas [MS PhD]

List of Research Topics and Ideas of VLSI for MS and Ph.D. Thesis.

1. High-throughput VLSI architecture for soft-decision decoding with ORBGRAND
2. Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing
3. ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture
4. Evaluating the Performances of Memristor, FinFET, and Graphene TFET in VLSI Circuit Design
5. VLSI mask optimization: From shallow to deep learning
6. Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal
7. A Novel High-Performance Hybrid Full Adder for VLSI Circuits
8. PGOpt: Multi-objective design space exploration framework for large-Scale on-chip power grid design in VLSI SoC using evolutionary computing technique
9. Testing single via related defectsin digital VLSI designs
10. An Improved Impulse Noise Removal VLSI Architecture Using DTBDM Method
11. VLSI Implementation of Multi-channel ECG Lossless Compression System
12. A Scalable VLSI Architecture for Illumination-Invariant Heterogeneous Face Recognition
13. Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support
14. Compact 3D Thermal Model for VLSI and ULSI Interconnect Network Reliability Verification
15. Simultaneous Parametric and Functional Testing of Digital VLSI During Radiation Experiments
16. A New 4-2 Compressor for VLSI Circuits and Systems
17. An ultra-low-power CNFET-based improved Schmitt trigger design for VLSI sensor applications
18. Performance Analysis of Clock Gating Designs in Low Power Vlsi Circuits
19. Flexible scheme for reconfiguring 2D mesh-connected VLSI subarrays under row and column rerouting
20. A Survey on VLSI Implementation of AES Algorithm with Dynamic S-Box
21. High-Throughput VLSI architecture for Soft-Decision decoding with ORBGRAND
22. Methods for Ensuring Full Traceability of the Production Testing Results of the Digital VLSI
23. Low Power Circuit Design for Footed Quasi Resistance Scheme In 45NM VLSI Technology
24. Fast Auto-Correction algorithm for Digital VLSI Circuits
25. Review of VLSI Architecture of Cryptography Algorithm for IOT Security
26. The VLSI Realization of Sign-Magnitude Decimal Multiplication Efficiency
27. Gate-Overlap Tunnel Field-Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications
28. VLSI design of a fast one-stage independent component extracting system based on ICA-R algorithm
29. Fully Reused VLSI Architectu Encoding for DSRC Applica
30. VLSI Architecture for DWT using 5/3 Wavelet Coefficient using Vedic Math’s
31. Design and vlsi implementation of a decimation filter for hearing aid applications
32. Analysis and Comparison of Leakage Power Reduction Techniques for VLSI Design
33. A low area VLSI implementation of extended tiny encryption algorithm using Lorenz chaotic system
34. Study and Analysis of Digital Counters for VLSI Applications
35. Synthesis of VLSI Structural Cell Partitioning Using Genetic Algorithm
36. VLSI Architecture for 8-bit Reversible Arithmetic Logic Unit based on Programmable Gate
37. Features of Designing Digital Processing Systems for Radiolocation Systems Based on Microprocessor VLSI Sets
38. Multiple-Criteria Decision Analysis Using VLSI Global Routing
39. Performance Evaluation of VLSI Implemented WSN Algorithms
40. Soft Error Rate Estimation of VLSI Circuits
41. Wave pipelined VLSI architecture for a Viterbi decoder using self reset logic with 0.65 nm technology
42. Efficient Band Offset Calculation Method for HEVC and Its VLSI Implementation
43. 2021 IEEE 39th VLSI Test Symposium (VTS)
44. A spike based learning neuron in analog VLSI
45. Computing Orientation of an Image by Projection Method and its VLSI Implementation
46. A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
47. The First Ge Nanosheets GAAFET CMOS Inverters Fabricated by 2D Ge/Si Multilayer Epitaxy, Ge/Si Selective Etching
48. Novel Architecture for Lifting Discrete Wavelet Packet Transform With Arbitrary Tree Structure
49. Back-Gate Network Extraction Free from Dynamic Self-Heating in FD SOI
50. Improvement of Nanotwinned Copper Thermal Stability for High Temperature Heterogeneous Integration
51. DFT Models of Ferroelectric Hafnium-Zirconium Oxide Stacks With and Without Dielectric Interlayers
52. Selective Area Epitaxy of Axial Wurtzite-InAs Nanowire on InGaAs NW by MOCVD
53. Calculation of Field Dependent Mobility in MoS2 and WS2 with Multi-Valley Monte Carlo Method
54. Ultra-thin Hf0.5Zr0.5O2 Ferroelectric Tunnel Junction with High Current Density
55. Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering
56. On-Wafer Electronic Layer Detectors Array (ELDA) for e-beam Imaging in Advanced Lithographic Systems
57. Contact engineered charge plasma junctionless transistor for suppressing tunneling leakage
58. Quantum Tunneling PUF: A Chip Fingerprint for Hardware Security
59. Ferroelectric and Antiferroelectric Hf/Zr oxide films: past, present and future
60. An Approach to Diminish the Leakage Power in Complementary MOS VLSI Circuits
61. Benchmarking the Performance of Heterogeneous Stacked RRAM with CFETSRAM and MRAM for Deep Neural Network Application Amidst Variation and Noise
62. Multi-bit cryogenic flash memory on Si/SiGe and Ge/GeSi heterostructures
63. Tensor-Centric Processor Architecture for Applications in Advanced Driver Assistance Systems
64. Evaluation de la complexit d’implantation en VLSI par la synth se architecturale: une exp rience en filtrage adaptatif
65. A precise debugging method and defect diagnosis with mass big-data analysis in the designed high-dense array for rapid yield improvement in a logic platform
66. Dynamic Mapping Mechanism to Compute DNN Models on a Resource-limited NoC Platform
67. Bandgap-Engineered Tunneling Layer on Operation Characteristics of Poly-Ge Charge-Trapping Flash Memory Devices
68. Reconfigurable Database Processor for Query Acceleration on FPGA
69. Holistic and In-Context Design Flow for 2.5 D Chiplet-Package Interaction Co-Optimization
70. ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design
71. Quantum dot celluar automata-based encoder and priority encoder circuits: Low latency and area efficient design
72. Shutdown mode implementation for Boost and Inverting Buck-Boost converter
73. AN ELEGANCE OF A NOVEL DIGITAL FILTER USING MAJORITY LOGIC FOR SNR IMPROVEMENT IN SIGNAL PROCESSING
74. Recent Progress on Flexible Capacitive Pressure Sensors: From Design and Materials to Applications
75. Prototypage d’algorithmes adaptatifs par un outil de synthèse d’architectures VLSI.
76. ALGORITMOS PARA PROBLEMAS DE STEINER COM APLICAÇÕES EM PROJETO DE CIRCUITOS VLSI
77. An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM
78. Prospective incorporation of booster in carbon interconnects for high-speed integrated circuits
79. Laser beam testing of finished integrated circuits
80. A survey of in-spin transfer torque mram computing
81. Oxytocin modulates neural processing of mitral/tufted cells in the olfactory bulb
82. Power Efficient Bit Lines: A Succinct Study
83. Introduction: Soft Error Modeling
84. Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation
85. Adiabatic Logic-Based Area-and Energy-Efficient Full Adder Design
86. Improved Noise Margin and Reduced Power Consumption in Subthreshold Adiabatic Logic Using Dual Rail Power Supply
87. IMPROVING SIZE-BOUNDS FOR SUBCASES OF SQUARE-SHAPED SWITCHBOX ROUTING
88. Design and Performance Evaluation of Highly Efficient Adders in Nanometer Technology
89. Qualitative and quantitative analysis of parallel-prefix adders
90. 4-Bit Ripple Carry Adder Using Area-Efficient Full Adder in CMOS Technology
91. Systolic-Architecture-Based Matrix Multiplications and Its Realization for Multi-Sensor Bias Estimation Algorithms
92. BiPart: a parallel and deterministic hypergraph partitioner
93. Dealing with Aging and Yield in Scaled Technologies
94. Ultraefficient imprecise multipliers based on innovative 4: 2 approximate compressors
95. A Low Power Approach for Designing 12-Bit Current Steering DAC
96. Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization
97. Gain-Cell Embedded DRAM Under Cryogenic Operation–A First Study
98. Communication and performance evaluation of 3-ary n-cubes onto network-on-chips
99. A New Function Mapping Approach in Defective Nanocrossbar Array Using Unique Number Sequence
100. Design, Simulation and Comparative Analysis of Performance Parameters of a 4-bit CMOS based Full Adder Circuit using Microwind and DSch at Various …
101. A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems
102. Leakage-Tolerant Low-Power Wide Fan-in OR Logic Domino Circuit
103. Carver Mead:” It’s All About Thinking,” A Personal Account Leading up to the First Microwave Transistor
104. Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller
105. An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder
106. Advanced Silicon & Semiconducting Silicon-Alloy Based Materials & Devices
107. A Novel Modeling-Attack Resilient Arbiter-PUF Design
108. Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links
109. Parallel algorithms
110. Transistor self-heating: The rising challenge for semiconductor testing
111. Adaptive Forward Body Bias Voltage Generator
112. PVT Aware Analysis of ISCAS C17 Benchmark Circuit
113. Hard-to-Detect Fault Analysis in FinFET SRAMs
114. Design and comparative analysis of on-chip sigma delta ADC for signal processing applications
115. Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs
116. Passivity-based non-fragile control of a class of uncertain fractional-order nonlinear systems
117. Impact of Spacers in Raised Source/Drain 14 nm Technology Node InGaAs-nFinFET on Short Channel Effects
118. High Speed Energy Efficient Multiplier Using 20nm FinFET Technology
119. Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits
120. Design and Analysis of 10T SRAM Cell with Stability Characterizations
121. Evaluation of Real-Time Embedded Systems in HILS and Delay Issues
122. Implementation and Analysis of Low Power Consumption Full Swing GDI Full Adders
123. A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory
124. [HTML][HTML] X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution
125. A New Improved V-Square-Controlled Buck Converter With Rail-to-Rail OTA-Based Current-Sensing Circuits
126. A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n-and p-type Flip-Flops
127. Variability Analysis of On-Chip Interconnect System Using Prospective Neural Network
128. Low Power NAND Gate–based Half and Full Adder/Subtractor Using CMOS Technique
129. Synchronization of mutual coupled fractional order one-sided lipschitz systems
130. Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders
131. Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme
132. High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register
133. High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone
134. Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique
135. Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator
136. Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V
137. Machine-learning-based self-tunable design of approximate computing
138. A novel current-controlled memristor-based chaotic circuit
139. Performance Analysis of MoS2FET for Electronic and Spintronic Application
140. Asynchronous Four-Phase and Two-Phase Circuits: Testing and Design for Testability
141. Controlling GIDL Using Core–Shell Technique in Conventional Nano-Wire
142. New FDNR and FDNC Simulation Configurations Using Inverted VDDIBAs
143. Optimal Mappings of the Spectrum of BPSK/QPSK Sequences to Finite Polynomial Fields and Rings
144. Impact of Multi-Metal Gate Stacks on the Performance of ß-Ga2O3 MOS Structure
145. On the Reliability of In-Memory Computing: Impact of Temperature on Ferroelectric TCAM
146. Design of Prominent Single-Precision 32-Bit Floating-Point Adder Using Single-Electron Transistor Operating at Room Temperature
147. HIPER: Low Power, High Performance and Area-Efficient Hardware Accelerators for Hidden Periodicity Detection using Ramanujan Filter Banks
148. A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation
149. Design of a new BUS for low power reversible computation
150. Controlling Mode Transition Noise Occurred at Ground Rail in Data Preserving MTCMOS Shift Register
151. Diversity Schemes in Multi-hop Visible Light Communications for 6G Networks
152. Fabrication of Micro-Compliant Mechanisms Using Micro-Stereolithography
153. A 27S/32S DC-balanced line coding scheme for PAM-4 signaling
154. Game Theory-based Parameter-Tuning for Path Planning of UAVs
155. A Low Latency Stochastic Square Root Circuit
156. New Resistorless FDNR Simulation Configuration Employing CDDITAs
157. An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0 V
158. Improved Store-Carry-Forward Scheme for Information Dissemination in Unfavorable Vehicular Distribution
159. Effect of surface modification treatment on top-pinned MTJ with perpendicular easy axis
160. Design and Implementation of an Efficient Mixed Parallel-Pipeline SAD Architecture for HEVC Motion Estimation
161. Negative Voltage Generator and Current DAC Based Regulator For Flash Memory
162. A non-autonomous chaotic system with no equilibrium
163. SIXOR: Single-Cycle In-Memristor XOR
164. Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
165. Towards energy-efficient STT-MRAM design with multi-modes reconfiguration
166. HT-IWT-DCT-Based Hybrid Technique of Robust Image Watermarking
167. GPU-Accelerated Soft Error Rate Analysis of Large-Scale Integrated Circuits
168. Performance Evaluation of Sub 5 nm GAA NWMBCFET using Silicon Carbide Source/Drain Material
169. A novel ultra-low power 7T full adder design using mixed logic
170. Reversible Fade Gate as Decoder, Encoder and Full Adder
171. A novel parallel prefix adder for optimized Radix-2 FFT processor
172. Smart Soldier Health Monitoring System Incorporating Embedded Electronics
173. Theoretical Analysis of Defected Ground Multiband Rectangular Shape Microstrip Patch Antenna
174. Design of Efficient Ternary Subtractor
175. Novel CDDITA-Based-Grounded Inductance Simulation Circuits
176. Trim Time Reduction in Analog/RF ICs Based on Inter-Trim Correlation
177. Ferroelectric HfO2 Memory Transistors with High-? Interfacial Layer and Write Endurance Exceeding 1010 Cycles
178. Design and Analysis of Low-Power SRAM
179. High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic
180. Selective Flip-Flop Optimization for Circuit Reliability
181. Effect of Developer Temperature on Photoresist Contrast in Grayscale Lithography
182. Power Series Representation Op logical Functions and its Applications to Error Detection and Error Correction Codes.(Dept. E)
183. Creating Fastest Self timing Reference Path for High Speed Memory Designs
184. Blockchain-enabled traceable, transparent transportation system for blood bank
185. Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System
186. Enhancement of ovonic threshold switching characteristics using nanometer-scale virtual electrode formed within ultrathin hafnium dioxide interlayer
187. Neural networks integrated circuit with switchable gait pattern for insect-type microrobot
188. Analog and Radio-Frequency Performance of Hetero-Gate-Dielectric FD SOI MOSFET in Re-S/D Technology
189. Stumped nature hyperjerk system with fractional order and exponential nonlinearity: Analog simulation, bifurcation analysis and cryptographic applications
190. Field-free and sub-ns magnetization switching of magnetic tunnel junctions by combining spin-transfer torque and spin–orbit torque
191. Fundamentals of microelectronics
192. Comparative Analysis of Channel Estimation Techniques in Vehicular Communication
193. Statistical analysis of vehicle detection in the ITS application for monitoring the traffic and road accident using internet of things
194. 3-D CMOS chip stacking for security ICs featuring backside buried metal power delivery networks with distributed capacitance
195. Sensor Localization in WSNs Using Rotating Directional-Antenna at the Base Station
196. A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications
197. FPGA implementation of fast digital FIR and IIR filters
198. Uniform 4-Stacked Ge0.9Sn0.1 Nanosheets Using Double Ge0.95Sn0.05 Caps by Highly Selective Isotropic Dry Etch
199. A 3–7 GHz CMOS Power Amplifier Design for Ultra-Wide-Band Applications
200. Fault-tolerant hamiltonian cycles and paths embedding into locally exchanged twisted cubes
201. Error-Controlling Technique in Wireless Communication
202. Human Action Recognition Using a New Hybrid Descriptor
203. Minimization of Peak-to-Average Power Ratio in DHT Precoded OFDM System by A-Law Companding
204. Machine Learning Oriented Dynamic Cost Factors-Based Routing in Communication Networks
205. Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning
206. Physical synthesis for advanced neural network processors
207. A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition
208. On the Best-Partition Communication Complexity
209. IMPLEMENTATION OF DIVISION AND SQUARE ROOT: MODELING AND EVALUATIONS
210. Structural and Optical Analysis of Bulk-Hetero Interface Between MoS2: Pentacene
211. Realization of a Low Profile, Wideband Omni-directional Antenna for Ku-band Airborne Applications
212. Ultracompact channel add-drop filter based on single multimode nanobeam photonic crystal cavity
213. Structural and Optical Characterization of EZO Thin Film for Application in Optical Waveguide
214. Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm
215. A Survey of Semantic Segmentation on Biomedical Images Using Deep Learning
216. PAPR Reduction in OFDM for VLC System
217. A Survey on Proactive and Reactive Channel Switching Techniques in Cognitive Radios
218. FPGA-based Hardware Acceleration for SVM Machine Learning Algorithm
219. Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy
220. A Multichannel Link-Layer Cooperation Protocol (MLCP) for Cognitive Radio Ad Hoc Network
221. AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction
222. Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling
223. A PVT aware differential delay circuit and its performance variation due to power supply noise
224. A Survey on Methodologies and Database Used for Facial Emotion Recognition
225. A Survey Study of Diseases Diagnosed Through Imaging Methodology Using Ultrasonography
226. Special Session: Physical Attacks through the Chip Backside: Threats, Challenges, and Opportunities
227. MOS based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance for biomedical applications: Analysis and proof of concept
228. Automated Simulator for the Validation of Bio-Impedance Devices
229. The Architectural Optimizations of a Low-Complexity and Low-Latency FFT Processor for MIMO-OFDM Communication Systems
230. An Optimal Design of 16 Bit ALU
231. Analysis of Power Adaptation Techniques Over Beaulieu-Xie Fading Model
232. Design and Analysis of Wearable Step-Shaped Sierpinski Fractal Antenna for WBAN Applications
233. ASSURE: RTL Locking Against an Untrusted Foundry
234. Design of Dynamic Induction Charging Vehicle for Glimpse of Future: Cutting Down the Need for High-Capacity Batteries and Charging Stations
235. Performance Analysis of Speck Cipher Using Different Adder Architectures
236. A Comparative Analysis of Statistical Model and Spectral Subtractive Speech Enhancement Algorithms
237. Dimensionality Reduction Using Principal Component Analysis for Lecture Attendance Management System
238. Design and implementation of current mode circuit for digital modulation
239. SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator
240. A Compact IPD Based on-Chip Bandpass Filter for 5G Radio Applications
241. An automated parallel simulation flow for cyber-physical system design
242. Conformal Omni Directional Antenna for GPS Applications
243. Recognition of Natural and Computer-Generated Images Using Convolutional Neural Network
244. SPIDER-based out-of-order execution scheme for Ht-MPSOC
245. Fast Encoding Using X-Search Pattern and Coded Block Flag Fast Method
246. Design and Simulation of a Dual-Band Radiometer for Humidity and Temperature Profiling
247. Voice Controlled IoT Based Grass Cutter Powered by Solar Energy
248. Periodic Octagon Split Ring Slot Defected Ground Structure for MIMO Microstrip Antenna
249. COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing
250. Design of Electronic Instrumentation for Isotope Processing
251. Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution
252. Design and analysis of improved high-speed adaptive filter architectures for ECG signal denoising
253. Compact and efficient structure of 8-bit S-box for lightweight cryptography
254. Virtually Doped Silicon-on-Insulator Junctionless Transistor for Reduced OFF-State Leakage Current
255. Reliability-Driven Voltage Optimization for NCFET-based SRAM Memory Banks
256. [HTML][HTML] Design and simulation of high-performance 2: 1 multiplexer based on side-contacted FED
257. Special Session–Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits
258. Enhancement of magnetic coupling and magnetic anisotropy in MTJs with multiple CoFeB/MgO interfaces for high thermal stability
259. Nonlinear Circuits and Systems with Memristors: Nonlinear Dynamics and Analogue Computing via the Flux-Charge Analysis Method
260. The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising
261. Information Theory-Based Defense Mechanism Against DDOS Attacks for WSAN
262. TxSim: Modeling training of deep neural networks on resistive crossbar systems
263. Automated Observability Analysis for Mixed-Signal Circuits
264. Silicon-on-nothing electrostatically doped junctionless tunnel field effect transistor (son-ed-jltfet): A short channel effect resilient design
265. Fault Detection and Classification in Microgrid Using Wavelet Transform and Artificial Neural Network
266. [HTML][HTML] Development of neural networks chip generating driving waveform for electrostatic motor
267. Computer Laboratory
268. Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing
269. Recent Development in Analytical Model for Graphene Field Effect Transistors for RF Circuit Applications
270. Phenomenological CNN model of a somatosensory effects
271. Reusability and Scalability of an SoC Testbench in Mixed-Signal Verification—The Inevitable Necessity
272. Power-and area-optimized high-level synthesis implementation of a digital down converter for software-defined radio applications
273. 3–21 GHz broadband and high linearity distributed low noise amplifier
274. 64-GHz datapath demonstration for bit-parallel SFQ microprocessors based on a gate-level-pipeline structure
275. Resynthesize Technique for Soft Error-Tolerant Design of Combinational Circuits
276. FPGA implementations for data encryption and decryption via concurrent and parallel computation: A review
277. Vertically integrated computing labs using open-source hardware generators and cloud-hosted FPGAs
278. Fast shared-memory streaming multilevel graph partitioning
279. Comparison of NMOS and PMOS Input Driving Dynamic Comparator in 45nm Technology
280. Hybrid Forecasting Model Based on Nonlinear Auto-Regressive Exogenous Network, Fourier Transform, Self-organizing Map and Pattern Recognition Model for Hour …
281. Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency
282. Design of Low Power Barrel Shifter Architecture by Using Proposed MUX Based CORDIC in CMOS Logic
283. Adaptive filtering algorithms in acoustic echo cancellation: a case study in architecure complexity evaluation
284. Performance improvement of elliptic curve cryptography system using low power, high speed 16× 16 Vedic multiplier based on reversible logic
285. Density Gradient Study on Junctionless Stack Nano-Sheet with Stack Gate Oxide for Low Power Application
286. All-digital built-in self-test scheme for charge-pump phase-locked loops
287. FPGA Hardware Acceleration of Soft Error Rate Estimation of Digital Circuits
288. Power-aware hold optimization for ASIC physical synthesis
289. Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits
290. New LMI Criterion to the Robust Stability of Discrete-Time Systems with Time-Varying Delays and Generalized Overflow Nonlinearities
291. A dual-mode successive approximation register analog to digital converter to detect malicious off-chip power noise measurement attacks
292. FPGA Design of SAR Type ADC Based Analog Input Module for Industrial Applications
293. Secure energy efficient network priority routing protocol for effective data collection and key management in dynamic WSNs
294. A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture
295. Monolithic 3D stacked multiply-accumulate units
296. Guidance-based improved depth upsampling with better initial estimate
297. Circuit and system-level aspects of phase change memory
298. An Active, Low-Power, 10Gbps, Current-based Transimpedance Amplifier in a Broadband Optical Receiver Front-End
299. Conception de deux points mémoire statiques CMOS durcis contre l’effet des aléas logiques provoqués par l’environnement radiatif spatial
300. Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits. Electronics 2021, 10 …
301. A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices
302. Design and Fabrication of a Polymer Microring Resonator: Polymer Microring Resonator
303. Design for Testability of Low Dropout Regulators
304. Magnonic band structure in CoFeB/Ta/NiFe meander-shaped magnetic bilayers
305. Novel Circuit Model of Multi-walled CNT Bundle Interconnects Using Multi-valued Ternary Logic
306. Higher-order Network Analysis Takes Off, Fueled by Classical Ideas and New Data
307. High-Level Synthesis of Custom DSP Blocks using Distributed Arithmetic
308. Enhancement-Mode Atomic-Layer-Deposited In2O3 Transistors With Maximum Drain Current of 2.2 A/mm at Drain Voltage of 0.7 V by Low-Temperature Annealing …
309. An Active, Low-Power, 10Gbps, Current-based Transimpedance Amplifier in a Broadband Optical Receiver Front-End
310. Design of High-Speed Binary Counter Architecture for Low-Power Applications
311. A Systematic Review on an Embedded Web Server Architecture
312. Build-in compact and efficient temperature sensor array on field programmable gate array
313. SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level
314. Low power, high-performance reversible logic enabled CNTFET SRAM cell with improved stability
315. Design and Verification of Advanced Microcontroller Bus Architecture-Advanced Peripheral Bus (AMBA-APB) Protocol
316. A Reconfigurable Architecture to Implement Linear Transforms of Image Processing Applications
317. Etude du bruit électrique en 1/f et des fluctuations RTS aux basses fréquences dans le transistor MOS submicronique
318. sonal communication, June 16, 1994.
319. In-memory realization of SHA-2 using ReVAMP architecture
320. Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range Query Over NVRAM
321. Design and validation of an artificial neural network based on analog circuits
322. Insight into threshold voltage and drain induced barrier lowering in negative capacitance field effect transistor
323. The past and future of multi-gate field-effect transistors: Process challenges and reliability issues
324. A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS……………….. K. Shiba …
325. [HTML][HTML] A Survey on Application Specific Processor Architectures for Digital Hearing Aids
326. A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era
327. Multilevel Hypergraph Partitioning with Vertex Weights Revisited
328. [HTML][HTML] The involution tool for accurate digital timing and power analysis
329. Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency. Electronics 2021, 10, 71
330. Memristor based high speed and low power consumption memory design using deep search method
331. Comparative Analysis of Adder for Various CMOS Technologies
332. Design of Parallel Sorting System Using Discrete-Time Neural Circuit Model
333. Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits
334. Process Variation-Aware Soft Error Rate Estimation Method for Integrated Circuits
335. Global placement with deep learning-enabled explicit routability optimization
336. Microcomputer Application in Motion Control
337. Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip
338. Capacitance-to-Digital Converter for Operation under Uncertain Harvested Voltage down to 0.3 V with No Trimming, Reference and Voltage Regulation
339. Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications
340. A Theoretical Study of Design Rewiring Using ATPG
341. FPGA Implementation of Bio-inspired Computing Based Deep Learning Model
342. Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators
343. Employing the Empirical Mode Decomposition to Denoise the Random Telegraph Noise
344. Dependence of metal gate work function variation for various ferroelectric thickness on electrical parameters in NC-FinFET
345. [HTML][HTML] A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs
346. Electronically tunable third-order dual-mode quadrature sinusoidal oscillators employing VDCCs and all grounded components
347. FPGA Implementation of Radix-4-Based Two-Dimensional FFT with and Without Pipelining Using Efficient Data Reordering Scheme
348. TRENDS IN DISTRIBUTED OBJECT COM-PUTING
349. Designing a New 4: 2 compressor using an efficient multi-layer full-adder based on nanoscale quantum-Dot cellular automata
350. Introduction to Dual Mode Logic (DML)
351. 3-D IC: An Overview of Technologies, Design Methodology, and Test Strategies
352. A Novel Plaintext-Related Color Image Encryption Scheme Based on Cellular Neural Network and Chen’s Chaotic System
353. Spatial Coverage of FM Radio Signal Variation Measurement and Comparison of two Major Radio Stations within Akwa Ibom State
354. Fabrication and selective wet etching of Si0. 2Ge0. 8/Ge multilayer for Si0. 2Ge0. 8 channel gate-all-around MOSFETs
355. High-performance area-efficient polynomial ring processor for CRYSTALS-Kyber on FPGAs
356. Dynamic workload allocation for edge computing
357. Non-volatile memory behavior of interfacial InOx layer in InAs nano-wire field-effect transistor for neuromorphic application
358. A Case Study on FPGA Implementation of Parts Counting Orientation Recognition Method for Industrial Vision System
359. A Survey of FIR Filter Design Techniques: Low-complexity, Narrow Transition-band and Variable Bandwidth
360. A low-power dynamic ternary full adder using carbon nanotube field-effect transistors
361. Design and analysis of (5, 10) regular LDPC encoder using MRP technique
362. Low-Voltage DML
363. Efficient Ternary Compressor Design Using Capacitive Threshold Logic in CNTFET Technology
364. Realization of 8 x 4 Barrel shifter with 4-bit binary to Gray converter using FinFET for Low Power Digital Applications
365. Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm
366. High-speed programmable photonic circuits in a cryogenically compatible, visible-NIR 200 mm CMOS architecture
367. S ntese de Alto N vel de Protocolos para a Abordagem IP sobre ATM
368. A Systematic Review of Approximate Adders: Accuracy and Performance Analysis
369. Evaluation of low power consumption network on chip routing architecture
370. Tiny robots and sensors need tiny batteries—here’s how to do it
371. Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation
372. Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications
373. Gradual magnetization switching via domain nucleation driven by spin–orbit torque
374. TEM studies during development of a 4-megabit DRAM
375. Circuit Design Using Genetic Programming: An Illustrative Study
376. Machine Learning for Electronic Design Automation: A Survey
377. Design optimization of sub-5 nm node nanosheet field effect transistors to minimize self-heating effects
378. Suppression of ambipolar behavior and simultaneous improvement in RF performance of gate-overlap tunnel field effect transistor (GOTFET) devices
379. Analysis on High-Performance Full Adders
380. Features of Organizing the Process of Designing Radar Microcircuits
381. Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar Arrays
382. On the role of system software in energy management of neuromorphic computing
383. Introduction to nanowires: types, proprieties, and application of nanowires
384. Unveiling the impact of the bias dependent charge neutrality point on graphene based multi transistor applications
385. True Random Number Generation using Latency Variations of Commercial MRAM Chips
386. Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures
387. Impact of the SiO2 interface layer on the crystallographic texture of ferroelectric hafnium oxide
388. Voltage-gate assisted spin-orbit torque magnetic random access memory for high-density and low-power embedded application
389. 1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing
390. Shift Left Trends for Design Convergence in SOC: An EDA Perspective
391. Domain wall mobility engineering by a perpendicular magnetic field in microwires with a gradient of perpendicular anisotropy
392. Characterization of QUBO reformulations for the maximum -colorable subgraph problem
393. State of charge estimation of lithium batteries in electric vehicles using IndRNN
394. Design of AES-Based Encryption Chip for IoT Security
395. A 15-bit, 5 MSPS SAR ADC with on-chip digital calibration
396. Optimization of Low Power LNA Using PSO for UWB Application
397. Amorphous InGaZnO Thin-Film Transistors With Sub-10-nm Channel Thickness and Ultrascaled Channel Length
398. Digital Implementation of Sigmoid Function in Artificial Neural Network Using VHDL
399. Performance Analysis for Tri-Gate Junction-Less FET by Employing Trioxide and Rectangular Core Shell (RCS) Architecture
400. Design of dopingless GaN nanowire FET with Low ‘Q’for high switching and RF applications
401. Circuit Design for Non-volatile Magnetic Memory
402. Post-Moore Memory Technology: Sneak Path Current (SPC) Phenomena on RRAM Crossbar Array and Solutions
403. An Energy-Efficient UWB Transmitter with Wireless Injection Locking for RF Energy-Harvesting Sensors
404. A Novel Structure and Operation Scheme of Vertical Channel NAND Flash with Ferroelectric Memory for Multi String Operations
405. Approximate Multipliers Using Bio-Inspired Algorithm
406. Fault-Tolerant Implementation of Quantum Arithmetic and Logical Unit (QALU) Using Clifford+T-Group
407. WADE: A Web-based Automated electronic Design Environment
408. Hybrid memristor-CMOS implementation of logic gates design using LTSpice.
409. Towards Scalable Spectral Embedding and Data Visualization via Spectral Coarsening
410. Half-Select Disturb-Free 10T Tunnel FET SRAM Cell with Improved Noise Margin and Low Power Consumption
411. Impact of Trapped-Charge Variations on Scaled Ferroelectric FET Nonvolatile Memories
412. A 4-GS/s 10-ENOB 75-mW ringamp ADC in 16-nm CMOS with background monitoring of distortion
413. Realization with fabrication of double-gate MOSFET based buck regulator
414. Two-dimensional transistors with reconfigurable polarities for secure circuits
415. A NEW DESIGN OF TANGENT HYPERBOLIC FUNCTION GENERATOR WITH APPLICATION TO THE NEURAL NETWORK IMPLEMENTATIONS
416. A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS
417. Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores
418. Electromigration in solder joints: A cross-sectioned model system for real-time observation
419. Design of Soft-Error-Aware SRAM With Multi-Node Upset Recovery for Aerospace Applications
420. M3DSSD: Monocular 3D single stage object detector
421. A ring oscillator with very low phase noise and wide frequency range using carbon nanotube technology for PLL applications
422. Towards Next Generation Robust Cryptosystems
423. Design and FPGA Synthesis of an Efficient Synchronous Counter with Clock-Gating Techniques
424. Layout dependence of total-ionizing-dose response in 65-nm bulk Si pMOSFET
425. Soft-error resilient read decoupled SRAM with multi-node upset recovery for space applications
426. On-Fly-TOD: an efficient mechanism for crosstalk fault reduction in WNoC
427. Experimental Examination of Component-Differentially-Challenged XOR PUF Circuits
428. Implementation of Neuro-Memristive Synapse for Long-and Short-Term Bio-Synaptic Plasticity
429. BiFeO3 clad modified fiber optic gas sensor for room temperature applications
430. AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs
431. Macrolide Biosensor Optimization through Cellular Substrate Sequestration
432. A design towards an energy-efficient and lightweight data security model in Fog Networks
433. Security of Neural Networks from Hardware Perspective: A Survey and Beyond
434. An Empirical Study of the Reliability of High-Level Synthesis Tools
435. Design of low-power coupled chopper instrumentation amplifier using pin pong ripple reduction for biomedical applications
436. Low Powered Self-Testable ALU
437. Nanopower multiple-input DTMOS OTA and its applications to high-order filters for biomedical systems
438. EM Lifetime Constrained Optimization for Multi-Segment Power Grid Networks
439. Approximate Array Multipliers
440. 2 Eduction
441. Linear k-arboricity of Caylay graphs on Abelian groups with given degree
442. ObfusX: routing obfuscation with explanatory analysis of a machine learning attack
443. FPGA-based architecture for bi-cubic interpolation: the best trade-off between precision and hardware resource consumption
444. Hardware Verification: Theory and Practice
445. Decomposition Methods of FSM Implementation
446. Word Length Selection Method for HIL power converter models
447. Review on performance analysis of P3HT: PCBM-based bulk heterojunction organic solar cells
448. Silico-Algorithmes et Arithm etique des Ordinateurs
449. Post-Moore Memory Technology: Sneak Path Current (SPC) Phenomena on RRAM Crossbar Array and Solutions. Micromachines 2021, 12, 50
450. On the Design of a Fault-Tolerant Scalable Three Dimensional NoC-Based Digital Neuromorphic System With On-Chip Learning
451. Electric Propulsion Methods for Small Satellites: A Review
452. Multi-Ferroic Properties on BiFeO3/BaTiO3 Multi-Layer Thin-Film Structures with the Strong Magneto-Electric Effect for the Application of Magneto-Electric Devices
453. A Systematic Review on Various Types of Full Adders
454. Superconducting neural networks with disordered Josephson junction array synaptic networks and leaky integrate-and-fire loop neurons
455. Benchmarking Machine Learning: How Fast Can Your Algorithms Go?
456. Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process
457. Multilevel Acyclic Hypergraph Partitioning*
458. Robust circuit implementation of 4-bit 4-tube CNFET based ALU at 16-nm technology node
459. Process validation test of CNTFET using Stanford model
460. Energy-aware routing considering load balancing for SDN: a minimum graph-based Ant Colony Optimization
461. Traffic sign detection optimization using color and shape segmentation as pre-processing system
462. Neuromorphic vision sensors: Principle, progress and perspectives
463. Binary Decision Diagrams
464. [HTML][HTML] Fast simulations of highly-connected spiking cortical models using GPUs
465. Dual Mode Logic in FD-SOI Technology
466. Spin–orbit torque and Dzyaloshinskii–Moriya interaction in perpendicularly magnetized heterostructures with iridium
467. On the Origin of Wake-Up and Antiferroelectric-Like Behavior in Ferroelectric Hafnium Oxide
468. Website Development for Trading Between Farmers and Government
469. Modeling and experimental analysis of an internally-cooled vapor chamber
470. Logic Synthesis of Sequential Logic Circuits for Adiabatic Quantum-Flux-Parametron Logic
471. Further stability analysis of neutral-type Cohen-Grossberg neural networks with multiple delays
472. Perspective on ferroelectric, hafnium oxide based transistors for digital beyond von-Neumann computing
473. Verilog Implementation of Biometric-Based Transmission of Fused Images Using Data Encryption Standards Algorithm
474. Learned smartphone isp on mobile npus with deep learning, mobile ai 2021 challenge: Report
475. Domain wall-magnetic tunnel junction spin–orbit torque devices and circuits for in-memory computing
476. Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node
477. Enhancing Security and Trust of IoT Devices–Internet of Secured Things (IoST)
478. Dual Metal Double Gate Ge-Pocket TFET (DMG-DG-Ge-Pocket TFET) with Hetero Dielectric: DC & Analog Performance Projections
479. DML Energy-Delay Tradeoffs and Optimization
480. Analysis and Design of On-Chip RF Interconnect Line for Wideband True-Time Delay Line Application
481. RECON: Resource-efficient CORDIC-based neuron architecture
482. A compensation textures dehazing method for water alike area
483. An Efficient Hardware Architecture for Deblocking Filter in HEVC
484. Toward novel designs of reversible ternary 6: 2 Compressor using efficient reversible ternary full-adders
485. 3D-aCortex: An ultra-compact energy-efficient neurocomputing platform based on commercial 3D-NAND flash memories
486. Study and Implementation of Ladder Logic Conversion to VHDL for Field Programmable Gate Array (FPGA)-Based Programmable Logic Controllers (PLC)
487. Enhanced Lubrication Ability of Polyalphaolefin and Polypropylene Glycol by COOH-Functionalized Multiwalled Carbon Nanotubes as an Additive
488. A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes
489. [HTML][HTML] Mathematical optimization approach for facility layout on several rows
490. Mobility enhancement techniques for Ge and GeSn MOSFETs
491. Towards the development of backing layer for piezoelectric micromachined ultrasound transducers
492. EN SYNTHESE D’ARCHITECTURE
493. Implementation of Autoencoders with Systolic Arrays through OpenCL
494. Ultra-high-performance magnetic nonvolatile level converter flip-flop with spin-hall assistance for dual-supply systems with power gating architecture
495. Adaptive Deconvolution-based stereo matching Net for Local Stereo Matching
496. Investigation of thick GaAs: Cr pixel sensors for X-ray imaging applications
497. Damage in silicon after reactive ion etching
498. Unraveling the optical contrast in Sb2Te and AgInSbTe phase-change materials
499. Emerging technologies and the security of western Europe
500. An overview of biological applications and fundamentals of new inlet and vacuum ionization technologies
501. Realization of a self-powered ZnSnO MSM UV photodetector that uses surface state controlled photovoltaic effect
502. Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles
503. Lowering the Schottky Barrier Height by Titanium Contact for High-Drain Current in Mono-layer MoS 2 Transistor
504. Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application
505. On the crossing numbers of join products of W_ {4}+ P_ {n} and W_ {4}+ C_ {n}
506. A Crystal-Less BLE Transmitter With Clock Recovery From GFSK-Modulated BLE Packets
507. Visibilidade em Poligonos utilizando algoritmos paralelos
508. Um Protocolo SR ARQ Ponto-a-Multiponto com Reconhecimento Acumulativo para Comunica cões a Altas Velocidades
509. Deep-Learning Assisted Compact Modeling of Nanoscale Transistor
510. Proposed pipeline clocking scheme for microarchitecture data propagation delay minimization
511. Ultralow-loss silicon nitride waveguides for nonlinear optics
512. [HTML][HTML] Benchmarking monolayer MoS 2 and WS 2 field-effect transistors
513. Phase Change Random Access Memory for Neuro-Inspired Computing
514. Security of Emerging Memory Chips
515. Study on Power Minimization techniques in SAR ADC Devices by Using Comparators Circuits
516. Built-In Self-Test (BIST) Methods for MEMS: A Review
517. AXON: NETWORK VIRTUAL STORAGE DESIGNz
518. IOT-HARPSECA: A Secure Design and Development System of Roadmap for Devices and Technologies in IOT Space
519. [HTML][HTML] High performance IIR filter implementation on FPGA
520. Terrestrial precise positioning system using carrier phase from burst signals and optically distributed time and frequency reference
521. Generation of Pseudorandom Sequence Using Regula-Falsi Method
522. A fractional-order CNN hyperchaotic system for image encryption algorithm
523. Genfloor: Interactive generative space layout system via encoded tree graphs
524. Our Perspectives
525. Transformations of Rectangular Dualizable Graphs
526. High-speed CMOS-compatible III-V on Si membrane photodetectors
527. Configurable DSI partitioned approximate multiplier
528. Stacking faults and precipitates in annealed and co-sputtered C49 TiSi2 films
529. Trading-o Power versus Area through a Parameterizable Model for Virtual Memory Manage
530. Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency
531. Internet Rescue Robots for Disaster Management [J]
532. Reliable advanced encryption standard hardware implementation: 32-bit and 64-bit data-paths
533. A new opportunity for the emerging tellurium semiconductor: resistive switching device implementation
534. [HTML][HTML] Simulation and experimental verification of modified sinusoidal pulse width modulation technique for torque ripple attenuation in Brushless DC motor drive
535. Ordered Binary Decision Diagrams, Gaussian Elimination and Graph Theory
536. Monitor Circuits for Cross-Layer Resiliency
537. TSV Fault Contactless Testing Method Based on Group Delay
538. [HTML][HTML] An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation
539. EBIC diffusion length of dislocated silicon
540. A 1-MS/s to 1-GS/s ringamp-based pipelined ADC with fully dynamic reference regulation and stochastic scope-on-chip background monitoring in 16 nm
541. A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS
542. Influence of High-Pressure Annealing Conditions on Ferroelectric and Interfacial Properties of Zr-Rich Hf?Zr1??O2Capacitors
543. Fault-based Built-in Self-test and Evaluation of Phase Locked Loops
544. Field-programmable gate arrays in a low power vision system
545. On undirected two-commodity integral flow, disjoint paths and strict terminal connection problems
546. Scheduling Conditional Nested Loops in a Resource Constrained ASIC Design
547. Reliability-Aware Multipath Routing of Time-Triggered Traffic in Time-Sensitive Networks
548. Time-domain computing in memory using spintronics for energy-efficient convolutional neural network
549. End-to-End Data Architecture Considerations for IoT
550. Covering problem on fuzzy graphs and its application in disaster management system
551. A Time-Frequency Measurement and Evaluation Approach for Body Channel Characteristics in Galvanic Coupling Intrabody Communication
552. Crosstalk minimization in network on chip (NoC) links with dual binary weighted code CODEC
553. A physical model for bulk gate insulator trap generation during bias-temperature stress in differently processed p-channel FETs
554. On the capabilities of Cellular Automata-based MapReduce model in Industry 4.0
555. Rail-to-rail dynamic voltage comparator scalable down to pw-range power and 0.15-v supply
556. In situ microsectioning and imaging of semiconductor devices using a scanning ion microscope
557. Estimation Probabiliste des Ressources, pour la synth ese d’Architectures
558. Improved design debugging architecture using low power serial communication protocols for signal processing applications
559. An enhanced cost-aware mapping algorithm based on improved shuffled frog leaping in network on chips
560. Single Event Transient (SET) Mitigation Circuits With Immune Leaf Nodes
561. A Period-Aware Routing Method for IEEE 802.1 Qbv TSN Networks
562. Special session: Reliability analysis for ML/AI hardware
563. The Japanese fifth generation computing project: curricular applications
564. Proposal for ultrafast all-optical pseudo random binary sequence generator using microring resonator-based switches
565. Hardware/Software Codesign for Energy Efficiency and Robustness: From Error-Tolerant Computing to Approximate Computing
566. TAAL: tampering attack on any key-based logic locked circuits
567. Hardware Trojan Prevention and Detection by Filling Unused Space Using Shift registers, Gate-chain and Extra Routing.
568. Quiet 2-Level Adiabatic Logic
569. Towards a DML Library Characterization and Design with Standard Flow
570. Sedenionic formulation for the field equations of multifluid plasma
571. Design and analysis of double-gate junctionless vertical TFET for gas sensing applications
572. Shared-Memory n-level Hypergraph Partitioning
573. An Improved Adaptive Genetic Algorithm for Two-Dimensional Rectangular Packing Problem
574. SRAMs
575. [HTML][HTML] Neuromorphic model of reflex for realtime human-like compliant control of prosthetic hand
576. Memory applications from 2D materials
577. Fast multipole method for 3-D Laplace equation in layered media
578. Dielectric spectroscopy and electrical conductivity measurements of a series of orthoconic antiferroelectric liquid crystalline esters
579. The unified modeling language reference manual
580. Design of a 2–30 GHz Low-Noise Amplifier: A Review
581. Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics
582. Early Detection of Prediabetes and T2DM Using Wearable Sensors and Internet-of-Things-Based Monitoring Applications
583. Road surface detection and differentiation considering surface damages
584. Deep learning-based feature extraction and optimizing pattern matching for intrusion detection using finite state machine
585. 2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local …
586. Uniform Crystal Formation and Electrical Variability Reduction in Hafnium-Oxide-Based Ferroelectric Memory by Thermal Engineering
587. REVIEW ON RUDIMENTS OF DIGITAL IMAGE PROCESSING
588. Computer simulation of X-ray topographs of curved silicon crystals
589. The analog/RF performance of a strained-Si graded-channel dual-material double-gate MOSFET with interface charges
590. Detecting Signature of Virus Using Metamaterial-Based One-Dimensional Multi-layer Photonic Crystal Structure Under Polarized Incidence
591. A DTMOS-based power efficient recycling folded cascode operational transconductance amplifier
592. Block coordinate descent based algorithm for computational complexity reduction in multichannel active noise control system
593. RRAM-Based Neuromorphic Computing Systems
594. analysis and Simulation of Schottky tunneling using Schottky barrier FET with 2-D analytical modeling
595. Investigation of Multiple-valued Logic Technologies for Beyond-binary Era
596. Structure and substructure connectivity of alternating group graphs
597. Power and area efficient stochastic artificial neural networks using spin–orbit torque-based true random number generator
598. Improvised hierarchy of Floating Point Multiplication using 5: 3 Compressor
599. Research on digital image watermark encryption based on hyperchaos
600. Calibration of WLI Lateral Indication Error with 2D Micro/Nano Pitch Standard
601. Implementation of Autoencoders with Systolic Arrays through OpenCL. Electronics 2021, 10, 70
602. State-of-the-Art TFET Devices
603. 1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology
604. Resilient and Secure Hardware Devices Using ASL
605. 6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency
606. Comparative Analysis of Rapid Single Flux Quantum (RSFQ) Circuit Technique Multipliers
607. BiCoSS: toward large-scale cognition brain with multigranular neuromorphic architecture
608. Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide.
609. TAN modelling of HH-shape microstrip interconnect tree
610. Improving efficiency in neural network accelerator using operands hamming distance optimization
611. Thickness of the subgroup intersection graph of a finite group [J]
612. A 189×600 Back-Illuminated Stacked SPAD Direct Time-of-Flight Depth Sensor for Automotive LiDAR Systems
613. A Fully Integrated 2.7 µW-70.2 dBm-Sensitivity Wake-Up Receiver with Charge-Domain Analog Front-End,-16.5 dB-SIR, FEC and Cryptographic Checksum
614. Learning complexity of simulated annealing
615. General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework
616. High Current Density in Monolayer MoS2 Doped by AlOx
617. A general semantics for logics of affirmation and negation
618. Symmetric-Mapping LUT-Based Method and Architecture for Computing XY-Like Functions
619. Modelling and Design of 5T, 6T and 7T SRAM Cell Using Deep Submicron CMOS Technology
620. [HTML][HTML] Coupled VO2 oscillators circuit as analog first layer filter in convolutional neural networks
621. Design of CMOS 6T and 8T SRAM for Memory Applications
622. Brain-inspired golden chip free hardware trojan detection
623. S ntese L ogica do Protocolo IPv6: Resultado de uma Metodologia visando o Projeto de Protocolos em Hardware
624. Influence of exposure energy and heat treatment conditions on through-glass via metallization of photoetchable glass interposers
625. A 0.8 V multimode vision sensor for motion and saliency detection with ping-pong PWM pixel
626. Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory
627. A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7 TOPS/W for Tiny AI Edge Devices
628. Electron beam induced artefact during TEM and Auger analysis of multilayer dielectrics
629. Binary precision neural network manycore accelerator
630. Deep learning-driven simultaneous layout decomposition and mask optimization

Computer Science Research Topics – MS PhD