Computer Architecture MCQs from latest Books edition

Computer Architecture MCQs from latest Books edition

1. Which registers of the processor are connected to Memory Bus?
A. PC
B. MAR
C. IR
D. Both PC and MAR

2. What is a collection of 8 bits called?
A. Byte
B. Word
C. Record
D. None of these

3. What does ISP stand for?
A. Interchange Standard Protocol
B. Interrupt Service Procedure
C. Instruction Set Processor
D. Information Standard Processing

4. What is the ascending order of a data Hierarchy?
A. Bytes -bit – record – field – file – database
B. Bytes – bit- field – record – file – database
C. Bit – bytes – record – field – file – database
D. Bit – bytes – fields – record – file – database

5. Internal components of the processor are connected by:
A. Rambus
B. Processor bus
C. Processor intra-connectivity circuitry
D. Memory bus

6. How much address lines are required to address each memory location in a 2048 x 4 memory chip?
A. 11
B. 12
C. 6
D. 14

7. What is used to choose between incrementing the PC or performing ALU operations?
A. Control unit
B. Conditional codes
C. Multiplexer
D. None of these

8. What is a computer program called that converts an entire program into machine language at one time?
A. Simulator
B. Interpreter
C. Commander
D. Compiler

9. The interconnection between ALU & Registers is collectively known as:
A. Information path
B. Data path
C. Process route
D. Information trail

10. Where does the operand is placed in immediate addressing?
A. After OP code in the instruction
B. In the CPU register
C. In stack
D. In memory

11. What is used to store data in registers?
A. JK flip-flop
B. RS flip-flop
C. D flip-flop
D. None of these

12. What are the interrupts which are initiated by an I/O drive?
A. Software
B. External
C. Internal
D. All of these

Read More Computer Architecture MCQs

1. 1. SET 1: Computer Architecture MCQs
   2. SET 2: Computer Architecture MCQs
   3. SET 3: Computer Architecture MCQs
   4. SET 4: Computer Architecture MCQs
   5. SET 5: Computer Architecture MCQs
   6. SET 6: Computer Architecture MCQs
   7. SET 7: Computer Architecture MCQs
   8. SET 8: Computer Architecture MCQs
   9. SET 9: Computer Architecture MCQs
   • Introduction to Computer Architecture MCQs
     • Evolution of Computer Architecture MCQs
     • von Neumann vs Harvard Architecture MCQs
   • Basic Components of a Computer System MCQs
     • Central Processing Unit (CPU) MCQs
     • Memory (RAM, ROM, Cache) MCQs
     • Input/Output (I/O) Devices MCQs
     • Buses (Data, Address, Control) MCQs
   • CPU Organization MCQs
     • ALU (Arithmetic Logic Unit) MCQs
     • Control Unit MCQs
     • Registers (General Purpose, Special Purpose) MCQs
     • Flags and Status Registers MCQs
   • Instruction Set Architecture (ISA) MCQs
     • Types of Instructions (Data Movement, Arithmetic, Control) MCQs
     • Addressing Modes (Immediate, Direct, Indirect, Indexed) MCQs
     • Instruction Formats MCQs
     • RISC (Reduced Instruction Set Computer) vs CISC (Complex Instruction Set Computer) MCQs
   • Microarchitecture MCQs
     • Pipelining (Stages and Hazards) MCQs
     • Superscalar Architecture MCQs
     • Multithreading MCQs
     • Out-of-Order Execution MCQs
   • Memory Hierarchy MCQs
     • Cache Memory (L1, L2, L3) MCQs
     • Virtual Memory MCQs
     • Paging and Segmentation MCQs
     • TLB (Translation Lookaside Buffer) MCQs
   • Cache Memory MCQs
     • Cache Mapping Techniques (Direct, Associative, Set-Associative) MCQs
     • Cache Coherency MCQs
     • Write Policies (Write-Through, Write-Back) MCQs
     • Cache Miss and Hit MCQs
   • Input/Output Organization MCQs
     • I/O Techniques (Polling, Interrupts, DMA) MCQs
     • I/O Mapping (Memory-Mapped I/O, Isolated I/O) MCQs
     • Interrupt Handling MCQs
   • Bus Architecture MCQs
     • System Bus (Data, Address, Control) MCQs
     • Bus Arbitration MCQs
     • Synchronous vs Asynchronous Buses MCQs
   • Performance Metrics MCQs
     • Clock Speed and Cycles per Instruction (CPI) MCQs
     • MIPS (Million Instructions per Second) MCQs
     • FLOPS (Floating-Point Operations per Second) MCQs
     • Amdahl’s Law MCQs
   • Parallelism in Computer Architecture MCQs
     • Instruction-Level Parallelism (ILP) MCQs
     • Data-Level Parallelism (DLP) MCQs
     • Thread-Level Parallelism (TLP) MCQs
     • Symmetric Multiprocessing (SMP) vs Asymmetric Multiprocessing (AMP) MCQs
   • Multicore and Multiprocessor Systems MCQs
     • Multicore Architectures MCQs
     • Shared Memory vs Distributed Memory MCQs
     • Interconnection Networks MCQs
   • Control Unit Design MCQs
     • Hardwired Control vs Microprogrammed Control MCQs
     • Control Signals and Timing MCQs
     • Instruction Cycle and Control Flow MCQs
   • Pipeline Hazards MCQs
     • Structural, Data, and Control Hazards MCQs
     • Techniques to Overcome Hazards (Stalling, Forwarding, Branch Prediction) MCQs
   • Branch Prediction and Speculation MCQs
     • Static and Dynamic Branch Prediction MCQs
     • Speculative Execution MCQs
     • Branch Target Buffers MCQs
   • Arithmetic and Logic Operations MCQs
     • Integer and Floating-Point Arithmetic MCQs
     • ALU Design MCQs
     • Fixed-Point vs Floating-Point Representation MCQs
   • Memory Management MCQs
     • Paging, Segmentation, and Virtual Memory MCQs
     • Memory Protection and Privilege Levels MCQs
     • Memory Allocation and Deallocation MCQs
   • Power and Energy Efficiency MCQs
     • Power Dissipation in CPUs MCQs
     • Low-Power Design Techniques MCQs
     • Energy-Aware Computing MCQs
   • Advanced Topics MCQs
     • GPU Architecture and Usage MCQs
     • Quantum Computing Basics MCQs
     • Neuromorphic Computing MCQs
   • Emerging Trends
     • Cloud Computing Architectures MCQs
     • Edge Computing MCQs
     • AI Accelerators MCQs