Pipelining (Stages and Hazards) MCQs

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1. What is instruction pipelining?
(A) Executing multiple instructions simultaneously
(B) Breaking down instruction execution into separate stages
(C) Fetching data from multiple sources
(D) Executing instructions serially

2. Which stage in the pipeline is responsible for fetching instructions from memory?
(A) Fetch
(B) Decode
(C) Execute
(D) Write-back

3. What does the decode stage in a pipeline do?
(A) Perform arithmetic calculations
(B) Fetch data from memory
(C) Interpret the fetched instruction
(D) Store the result

4. Which of the following is NOT a typical pipeline stage?
(A) Fetch
(B) Decode
(C) Write-back
(D) Interrupt

5. What is the primary benefit of pipelining?
(A) Reduce instruction size
(B) Increase instruction throughput
(C) Simplify instruction execution
(D) Decrease clock speed

6. What is a pipeline hazard?
(A) A delay caused by dependencies between instructions
(B) A performance boost in the pipeline
(C) The completion of an instruction stage
(D) An error in memory fetching

7. What is a data hazard in pipelining?
(A) When two instructions need the same resource
(B) When the wrong instruction is fetched
(C) When an instruction depends on the result of a previous instruction
(D) When the pipeline fails

8. Which of the following is a control hazard?
(A) When the pipeline fetches the wrong instruction due to a branch
(B) When two instructions access the same memory
(C) When an instruction is executed out of order
(D) When there is a delay in the write-back stage

9. What is a structural hazard in pipelining?
(A) When an instruction depends on data not yet computed
(B) When two instructions compete for the same hardware resource
(C) When the pipeline stalls due to a branch misprediction
(D) When the ALU fails

10. What is pipeline stall?
(A) When the CPU runs out of power
(B) When the pipeline fetches an instruction from memory
(C) When instructions are executed in parallel
(D) When a pipeline stage is delayed and the next stage has to wait

11. How can data hazards be resolved in a pipelined processor?
(A) Flushing the pipeline
(B) Instruction reordering
(C) Using the same memory for data and instructions
(D) Adding more pipeline stages

12. What is instruction-level parallelism (ILP)?
(A) Executing multiple instructions simultaneously within a pipeline
(B) Executing instructions sequentially
(C) Writing data to memory
(D) Decoding multiple instructions at once

13. What is forwarding (also known as bypassing) used for in a pipeline?
(A) To prevent branch mispredictions
(B) To reduce the impact of data hazards by passing data directly to dependent stages
(C) To speed up the fetch stage
(D) To combine multiple instructions into one

14. What is branch prediction used for in pipelining?
(A) To execute instructions in reverse order
(B) To execute branches in parallel
(C) To reorder instructions
(D) To guess the outcome of a branch instruction before it is resolved

15. What happens if a branch is mispredicted in a pipeline?
(A) The pipeline continues execution as normal
(B) The pipeline must be flushed, and the correct instructions fetched
(C) The CPU shuts down
(D) The incorrect branch is executed

16. Which technique can help reduce control hazards in pipelining?
(A) Instruction prefetching
(B) Data forwarding
(C) Branch prediction
(D) Cache coherence

17. What is meant by pipeline depth?
(A) The number of ALUs in the CPU
(B) The amount of data processed per cycle
(C) The number of instructions processed simultaneously
(D) The number of stages in the pipeline

18. What is pipeline interlocking?
(A) A technique to prevent simultaneous access to the same hardware resource
(B) A method to reduce instruction fetches
(C) A mechanism to stop the pipeline until hazards are resolved
(D) A way to execute instructions out of order

19. How can structural hazards in a pipeline be minimized?
(A) Using branch prediction
(B) Increasing the number of functional units
(C) Reordering instructions
(D) Using a deeper pipeline

20. What is the function of the execute stage in a pipeline?
(A) Perform instruction decoding
(B) Execute the operation specified by the instruction
(C) Write data to memory
(D) Fetch instructions

21. Which pipeline stage writes the result of an instruction back to the register file?
(A) Fetch
(B) Execute
(C) Decode
(D) Write-back

22. What does it mean when a pipeline has a bubble?
(A) There is an empty slot in the pipeline due to a stall
(B) An instruction is executed incorrectly
(C) The pipeline is flushed
(D) Instructions are being executed in parallel

23. What is the purpose of the fetch stage in a pipeline?
(A) Execute the instruction
(B) Fetch the next instruction from memory
(C) Store the result in memory
(D) Decode the instruction

24. How does pipelining improve CPU performance?
(A) By decreasing the instruction size
(B) By allowing multiple instructions to be processed simultaneously at different stages
(C) By increasing clock speed
(D) By reducing power consumption

25. What is a load-use data hazard?
(A) A hazard that occurs when a load instruction is followed by an instruction that uses the loaded data
(B) A hazard caused by storing data
(C) A control hazard in the decode stage
(D) A structural hazard due to limited memory access

26. Which of the following is a method to handle branch hazards in pipelining?
(A) Instruction prefetching
(B) Instruction bypassing
(C) Pipeline flushing
(D) Register renaming

27. What is the role of the decode stage in pipelining?
(A) Write the results to memory
(B) Convert the fetched instruction into control signals
(C) Execute the instruction
(D) Fetch the next instruction

28. How does pipeline flushing affect performance?
(A) It increases performance by removing hazards
(B) It speeds up instruction execution
(C) It has no effect on performance
(D) It reduces performance due to wasted clock cycles

29. What is a branch delay slot?
(A) A delay introduced after a branch instruction to resolve the branch
(B) The time taken for a branch to be resolved
(C) An extra cycle added to execute a branch
(D) A method of instruction reordering

30. What is the role of an instruction queue in pipelining?
(A) To store intermediate results from the ALU
(B) To hold instructions before they enter the pipeline
(C) To predict branch outcomes
(D) To reorder instructions

31. What does dynamic scheduling do in a pipeline?
(A) It reduces the number of stages in the pipeline
(B) It decodes multiple instructions at once
(C) It flushes the pipeline after each instruction
(D) It schedules instructions based on the availability of resources to avoid hazards

32. What is speculative execution in pipelining?
(A) Executing instructions in the correct order
(B) Guessing the outcome of instructions and executing them before they are confirmed
(C) Stalling the pipeline when hazards occur
(D) Writing results to memory early

33. What is the difference between static and dynamic branch prediction?
(A) Static prediction always makes the same guess, while dynamic prediction adapts based on past behavior
(B) Static prediction is faster than dynamic prediction
(C) Dynamic prediction is only used for structural hazards
(D) Static prediction guesses based on memory access, while dynamic prediction guesses based on data

34. What does the term “out-of-order execution” mean in pipelining?
(A) Instructions are executed in the order they are fetched
(B) Instructions are executed in the order of their priority
(C) Instructions are executed as soon as their operands are available, regardless of their original order
(D) Instructions are reordered in memory before being executed

35. Which technique can be used to handle structural hazards?
(A) Cache memory
(B) Instruction prefetching
(C) Branch prediction
(D) Increasing the number of execution units

36. What is meant by register renaming in pipelining?
(A) Reordering instructions to avoid register conflicts
(B) Using different physical registers to avoid data hazards
(C) Renaming instructions for better clarity
(D) Swapping registers between different stages

37. Which of the following is a typical symptom of a pipeline bubble?
(A) Increased power consumption
(B) Faster instruction execution
(C) Decreased instruction throughput
(D) Decreased clock speed

38. What is a branch target buffer (BTB)?
(A) A cache for storing predicted branch addresses
(B) A unit for performing branch instructions
(C) A technique to reduce structural hazards
(D) A buffer for holding the result of branch instructions

39. How does instruction reordering help with data hazards?
(A) It increases the clock speed
(B) It eliminates the need for branch prediction
(C) It combines multiple instructions into one
(D) It allows independent instructions to be executed while waiting for data

40. What is the role of the instruction decode stage in the pipeline?
(A) Fetch the next instruction from memory
(B) Convert the instruction into control signals for execution
(C) Write the result to memory
(D) Execute the instruction directly

41. What is meant by a pipeline flush?
(A) Clearing all instructions from the pipeline
(B) Executing instructions in parallel
(C) Storing the result in memory
(D) Prefetching multiple instructions

42. Which of the following helps minimize branch hazards?
(A) Dynamic scheduling
(B) Data forwarding
(C) Instruction cache
(D) Branch prediction

43. What does pipeline depth refer to?
(A) The number of stages in the pipeline
(B) The number of instructions executed per clock cycle
(C) The amount of data stored in registers
(D) The time taken to execute one instruction

44. What is a RAW (Read After Write) hazard?
(A) When two instructions write to the same register
(B) When data is read from memory before it is written
(C) When an instruction needs data that has not yet been written
(D) When data is written to memory twice

45. What is the function of a reorder buffer in pipelining?
(A) To reorder data in the cache
(B) To store instructions before they are executed
(C) To predict branches
(D) To hold results until instructions are ready to be committed in order

46. How does out-of-order execution affect performance?
(A) It reduces performance by increasing hazards
(B) It has no impact on performance
(C) It improves performance by allowing independent instructions to be executed when ready
(D) It eliminates the need for pipelining

47. What is a WAW (Write After Write) hazard?
(A) When two instructions try to write to the same register at the same time
(B) When data is written to memory twice in a row
(C) When data is read from memory after it has been written
(D) When an instruction depends on data that has not been read yet

48. How does pipeline forwarding work?
(A) It sends data directly between pipeline stages to avoid hazards
(B) It fetches instructions early to avoid stalls
(C) It writes the result to memory before execution is complete
(D) It flushes the pipeline when hazards occur

49. What does pipeline latency refer to?
(A) The time taken to fetch an instruction from memory
(B) The number of instructions executed per cycle
(C) The delay caused by data hazards
(D) The time taken to complete all stages of an instruction

50. How can pipeline bubbles be minimized?
(A) By using deeper pipelines
(B) By improving branch prediction accuracy
(C) By reducing the number of functional units
(D) By decreasing clock speed

Pipelining (Stages and Hazards) MCQs

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