Microprocessor and computer architecture MCQs Quizlet 

By: Prof. Dr. Fazal Rehman | Last updated: September 20, 2024

Microprocessor and computer architecture MCQs Quizlet 

1.  A dedicated computer is a computer that is assigned with …

a) only one task at a time

b) multiple task at a time

c) used by multiple person

d) none of these

2. Interrupts initiated by I/O devices are basically

a) external

b) internal

c) intrinsic

d) none of these

3. Which operations are performed by microprograms?

a) read

b) execute

c) right

d) read and execute

4. Where the operand is placed in the immediate addressing?

a) after OP code

b) before OP code

c) in CPU register

d) none of these

5. Which computer program is used to convert whole program into the machine lagnuage at a time ?

a) simulator

b) compiler

c) interpreter

d) commander

6. Which one of the operation is implemented by pipeline?

a) fetch array

b) code instruction

c) execute instruction

d) none of these

7. SRAM’s can be used as

a) caches

b) registers

c) buffer

d) TLB’s

8. Why we use higher order bits of addressess?

a) specify table address

b) specify row address

c) specify column address

d) none of these

9. Multiplexed signals of the controller are splitted as …

a) RAS and CAS

b) CAS and NAS

c) MAS and PAS 

d) EAS and RAC

10. A program is divided into parts for the ease of execution named as …

a) fragments

b) segments

c) pages

d) sheets

11. The binary address issued to the instructions and data is known as …

a) location address

b) physical address

c) logical address

d) none of these

12. MMU stands for

a) Memory Management Unit

b) Memory Model Unit

c) Memory Manipulation Unit

d) none of these

Read More Computer Architecture MCQs

1. SET 1: Computer Architecture MCQs
2. SET 2: Computer Architecture MCQs
3. SET 3: Computer Architecture MCQs
4. SET 4: Computer Architecture MCQs
5. SET 5: Computer Architecture MCQs
6. SET 6: Computer Architecture MCQs
7. SET 7: Computer Architecture MCQs
8. SET 8: Computer Architecture MCQs
9. SET 9: Computer Architecture MCQs

• Introduction to Computer Architecture MCQs
  • Evolution of Computer Architecture MCQs
  • von Neumann vs Harvard Architecture MCQs
• Basic Components of a Computer System MCQs
  • Central Processing Unit (CPU) MCQs
  • Memory (RAM, ROM, Cache) MCQs
  • Input/Output (I/O) Devices MCQs
  • Buses (Data, Address, Control) MCQs
• CPU Organization MCQs
  • ALU (Arithmetic Logic Unit) MCQs
  • Control Unit MCQs
  • Registers (General Purpose, Special Purpose) MCQs
  • Flags and Status Registers MCQs
• Instruction Set Architecture (ISA) MCQs
  • Types of Instructions (Data Movement, Arithmetic, Control) MCQs
  • Addressing Modes (Immediate, Direct, Indirect, Indexed) MCQs
  • Instruction Formats MCQs
  • RISC (Reduced Instruction Set Computer) vs CISC (Complex Instruction Set Computer) MCQs
• Microarchitecture MCQs
  • Pipelining (Stages and Hazards) MCQs
  • Superscalar Architecture MCQs
  • Multithreading MCQs
  • Out-of-Order Execution MCQs
• Memory Hierarchy MCQs
  • Cache Memory (L1, L2, L3) MCQs
  • Virtual Memory MCQs
  • Paging and Segmentation MCQs
  • TLB (Translation Lookaside Buffer) MCQs
• Cache Memory MCQs
  • Cache Mapping Techniques (Direct, Associative, Set-Associative) MCQs
  • Cache Coherency MCQs
  • Write Policies (Write-Through, Write-Back) MCQs
  • Cache Miss and Hit MCQs
• Input/Output Organization MCQs
  • I/O Techniques (Polling, Interrupts, DMA) MCQs
  • I/O Mapping (Memory-Mapped I/O, Isolated I/O) MCQs
  • Interrupt Handling MCQs
• Bus Architecture MCQs
  • System Bus (Data, Address, Control) MCQs
  • Bus Arbitration MCQs
  • Synchronous vs Asynchronous Buses MCQs
• Performance Metrics MCQs
  • Clock Speed and Cycles per Instruction (CPI) MCQs
  • MIPS (Million Instructions per Second) MCQs
  • FLOPS (Floating-Point Operations per Second) MCQs
  • Amdahl’s Law MCQs
• Parallelism in Computer Architecture MCQs
  • Instruction-Level Parallelism (ILP) MCQs
  • Data-Level Parallelism (DLP) MCQs
  • Thread-Level Parallelism (TLP) MCQs
  • Symmetric Multiprocessing (SMP) vs Asymmetric Multiprocessing (AMP) MCQs
• Multicore and Multiprocessor Systems MCQs
  • Multicore Architectures MCQs
  • Shared Memory vs Distributed Memory MCQs
  • Interconnection Networks MCQs
• Control Unit Design MCQs
  • Hardwired Control vs Microprogrammed Control MCQs
  • Control Signals and Timing MCQs
  • Instruction Cycle and Control Flow MCQs
• Pipeline Hazards MCQs
  • Structural, Data, and Control Hazards MCQs
  • Techniques to Overcome Hazards (Stalling, Forwarding, Branch Prediction) MCQs
• Branch Prediction and Speculation MCQs
  • Static and Dynamic Branch Prediction MCQs
  • Speculative Execution MCQs
  • Branch Target Buffers MCQs
• Arithmetic and Logic Operations MCQs
  • Integer and Floating-Point Arithmetic MCQs
  • ALU Design MCQs
  • Fixed-Point vs Floating-Point Representation MCQs
• Memory Management MCQs
  • Paging, Segmentation, and Virtual Memory MCQs
  • Memory Protection and Privilege Levels MCQs
  • Memory Allocation and Deallocation MCQs
• Power and Energy Efficiency MCQs
  • Power Dissipation in CPUs MCQs
  • Low-Power Design Techniques MCQs
  • Energy-Aware Computing MCQs
• Advanced Topics MCQs
  • GPU Architecture and Usage MCQs
  • Quantum Computing Basics MCQs
  • Neuromorphic Computing MCQs
• Emerging Trends
  • Cloud Computing Architectures MCQs
  • Edge Computing MCQs
  • AI Accelerators MCQs