Multiple choice of DLD

1. __________ is suitable for testing the odd parity of word.

A.AND gate
B.OR gate
C.NOR gate
D.XOR gate

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2. Due to change in one input variable, different internal variable change, this makes ____________.
A. Hold delay
B. Hold and Wait
C. Clock Skew
D. Race condition
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3. In asynchronous circuit _____________ is responsible for occurring changes.
A. clock pulse
B. input
C. output
D. time
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4. _________________will give the sum of full adders as output.
A.Three-point majority circuit
B.Three-bit parity checker
C.Three bit counter
D.Three-bit comparator
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5. Which of the following input overrides other?
A. Asynchronous override synchronous
B. Synchronous override asynchronous
C. Clear input override Preset input
D. Preset input override Clear input
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6. Present state is determined in synchronous circuits by_____________
A. flip-flops
B. clocked flip-flops
C. Unlocked flip-flops
D. latches
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7. How many number of full and half-adders required to add 16-bit number?
A.8 half-adders, 8 full-adders
B.16 half-adders, 0 full-adders
C.1 half-adder, 15 full-adders
D.4 half-adders, 12 full-adders
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8. __________ is a decade counter.
A. Mod-10 counter
B. Mod-5 counter
C. Mod-8 counter
D. Mod-3 counter
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9. The state of Present and next of asynchronous circuits are also known as ____________
A. primary variables
B. secondary variables
C. excitation variables
D. short term memory
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10. From maximum value the time required to a pulse to decrease from 90% to 10% is known as ____________.
A.Decay time
B.Rise time
C.Binary level transition period
D.Propagation delay
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11. Where is the logic set when the transmission line is idle in the asynchronous transmission?
A. Remains in the previous state
B. It is set to logic low
C. It is set to logic high
D. State of the transmission line is not used to start transmission
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12. In ________________ stable state depends on order.
A. defined race
B. identical race
C. non critical race
D. critical race
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MCQs of Digital Logic Design (DLD)

Introduction to Digital Systems

  1. Analog vs. Digital signals MCQs
  2. Binary numbers and arithmetic MCQs
  3. Logic levels and noise margins MCQs

Boolean Algebra

  1. Basic logic operations (AND, OR, NOT) MCQ
  2. Laws and theorems of Boolean algebra MCQ
  3. De Morgan’s Theorems MCQ
  4. Canonical forms (Sum of Products, Product of Sums) MCQ
  5. Simplification techniques (Karnaugh Maps, Quine-McCluskey method) MCQ

Combinational Logic

Logic Gates

  1. Basic gates (AND, OR, NOT) Gat MCQ
  2. Universal gates (NAND, NOR) Gat MCQs
  3. XOR and XNOR gates MCQ

Combinational Circuits

  1. Design and analysis of combinational circuits MCQ
  2. Multiplexers and Demultiplexers MCQ
  3. Encoders and Decoders MCQ
  4. Binary Adders (Half adder, Full adder) MCQ
  5. Subtractors and Arithmetic Logic Units (ALU) MCQ
  6. Comparators MCQ in DLD

Sequential Logic

Flip-Flops and Latches

  1. SR Latch, D Latch MCQ
  2. Flip-Flops (SR, D, JK, T) MCQ
  3. Characteristic equations and excitation tables MCQ
  4. Edge-triggered vs. level-triggered devices MCQ

Counters and Registers

  1. Synchronous, Asynchronous (ripple), Up/Down counters MCQs
  2. Shift registers (SIPO, PISO, SISO, PIPO) MCQs

State Machines

Finite State Machines (FSMs)

  1. Moore and Mealy machines MCQs

Memory and Programmable Logic MCQs

Memory Devices

  1. Read-Only Memory (ROM)
  2. Random Access Memory (RAM)
  3. Programmable Logic Devices (PLDs) MCQs
  4. Field Programmable Gate Arrays (FPGAs) MCQs

More MCQs of Digital Logic Design (DLD)

Computer Science Repeated MCQs Book Download

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