MCQs of DLD
1. Which of the following gates give output 1, if and only if at least one input is 1?
A.OR
B.AND
C.NOR
D.NAND
2. For performing the function of twoinput OR gate, What is the minimum number of twoinput NAND gates used?
A.2
B.3
C.4
D.5
3. In an application where input signals may ________________,Asynchronous circuits are useful.
A. never change
B. change at any time
C. both a and b
D. None
4. The time required by a gate or inverter to change their state is called _______________.
A.Rise time
B.Decay time
C.Charging time
D.Propagation time
5. The next state is determined in a sequential circuit is determined by ________ and _______
A. Current state and external input
B. Current state, flipflop output
C. State variable, current state
D. Input and clock signal applied
6. SR latch contain ______________
A. 4 input
B. 3 inputs
C. 2 inputs
D. 1 inputs
7. If a pulse change from 10% to 90% of its maximum value, the time required is known as _____________.
A.Rise time
B.Operating speed
C.Propagation time
D.Decay time
8. By using two cascading counters _____________, ____________ the divideby60 counter in digital clock is implemented.
A. Mod10, Mod50.
B. Mod50, Mod10
C. Mod6, Mod10
D. Mod50, Mod6
9. Which table is not a part of the asynchronous analysis procedure?
A. transition table
B. excitation table
C. flow table
D. state table
10. Digital data can be applied to gate by maximum frequency which is called _________________.
A. Charging time
B. Propagation speed
C. Binary level transaction period
D. Operating speed
11. Minimum time for which input signal maintained at the input of flipflop is called _____________ of the flipflop.
A. Setup time
B. Hold time
C. Pulse Stability time (PST)
D. Pulse Interval time
12. For making a transition table we use _____________.
A. 3 steps
B. 5 steps
C. 6 steps
D. 8 steps
MCQs of Digital Logic Design (DLD)
Introduction to Digital Systems
 Analog vs. Digital signals MCQs
 Binary numbers and arithmetic MCQs
 Logic levels and noise margins MCQs
Boolean Algebra
 Basic logic operations (AND, OR, NOT) MCQ
 Laws and theorems of Boolean algebra MCQ
 De Morgan’s Theorems MCQ
 Canonical forms (Sum of Products, Product of Sums) MCQ
 Simplification techniques (Karnaugh Maps, QuineMcCluskey method) MCQ
Combinational Logic
Logic Gates
Combinational Circuits
 Design and analysis of combinational circuits MCQ
 Multiplexers and Demultiplexers MCQ
 Encoders and Decoders MCQ
 Binary Adders (Half adder, Full adder) MCQ
 Subtractors and Arithmetic Logic Units (ALU) MCQ
 Comparators MCQ in DLD
Sequential Logic
FlipFlops and Latches
 SR Latch, D Latch MCQ
 FlipFlops (SR, D, JK, T) MCQ
 Characteristic equations and excitation tables MCQ
 Edgetriggered vs. leveltriggered devices MCQ
Counters and Registers
 Synchronous, Asynchronous (ripple), Up/Down counters MCQs
 Shift registers (SIPO, PISO, SISO, PIPO) MCQs
State Machines
Finite State Machines (FSMs)
Memory and Programmable Logic MCQs
Memory Devices
 ReadOnly Memory (ROM)
 Random Access Memory (RAM)
 Programmable Logic Devices (PLDs) MCQs
 Field Programmable Gate Arrays (FPGAs) MCQs
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 SET 6:DLD MCQs DLD Solved MCQs Answers PDF
MCQs collection of solved and repeated MCQs with answers for the preparation of competitive exams, admission test and job of PPSC, FPSC, UPSC, AP, APPSC, APSC, BPSC, PSC, GOA, GPSC, HPSC, HP, JKPSC, JPSC, KPSC, KERALAPSC, MPPSC, MPSC, MPSCMANIPUR, MPSC, NPSC, OPSC, RPSC, SPSCSKM, TNPSC, TSPSC, TPSC, UPPSC, UKPSC, SPSC, KPPSC, BPSC, AJKPSC ALPSC, NPSC, LPSC, SCPSC, DPSC, DCPSC, PSC, UPSC, WVPSC, PSCW, and WPSC.