MCQs of DLD
1. Which of the following gates give output 1, if and only if at least one input is 1?
2. For performing the function of two-input OR gate, What is the minimum number of two-input NAND gates used?
3. In an application where input signals may ________________,Asynchronous circuits are useful.
A. never change
B. change at any time
C. both a and b
4. The time required by a gate or inverter to change their state is called _______________.
5. The next state is determined in a sequential circuit is determined by ________ and _______
A. Current state and external input
B. Current state, flip-flop output
C. State variable, current state
D. Input and clock signal applied
6. SR latch contain ______________
A. 4 input
B. 3 inputs
C. 2 inputs
D. 1 inputs
7. If a pulse change from 10% to 90% of its maximum value, the time required is known as _____________.
8. By using two cascading counters _____________, ____________ the divide-by-60 counter in digital clock is implemented.
A. Mod-10, Mod-50.
B. Mod-50, Mod-10
C. Mod-6, Mod-10
D. Mod-50, Mod-6
9. Which table is not a part of the asynchronous analysis procedure?
A. transition table
B. excitation table
C. flow table
D. state table
10. Digital data can be applied to gate by maximum frequency which is called _________________.
A. Charging time
B. Propagation speed
C. Binary level transaction period
D. Operating speed
11. Minimum time for which input signal maintained at the input of flip-flop is called _____________ of the flip-flop.
A. Set-up time
B. Hold time
C. Pulse Stability time (PST)
D. Pulse Interval time
12. For making a transition table we use _____________.
A. 3 steps
B. 5 steps
C. 6 steps
D. 8 steps
More MCQs of Digital Logic Design (DLD)
SET 1: dld mcqs with answers (dld mcqs with answers)
SET 2: dld basic mcqs (dld basic mcqs)
SET 3: solved mcqs of dld (solved mcqs of dld)
SET 4: dld repeated mcqs (dld repeated mcqs)
SET 5: dld importan mcqs (dld importan mcqs)