MCQs Digital Logic Design
1. When we input two values 0 and 1 which of the following gates would output 1?
A. OR gate
B. NAND gate
C. AND gate
D. both a and c
2. one nibble= ________ bits
A. 16
B. 8
C. 4
D. 2
3. flip-flops that are unlocked are called
A. Transition tables
B. register
C. Latches
D. None
4. Which is not equal to x?
A. X NAND 1
B. X NOR X
C. X NAND X
D. X NOR 1
5.What value Excess-8 code assigns to “-8”?
A. 0000
B. 1100
C. 1110
D. 1000
6. How many rows are needed in the primitive flow table for the gated latch?
A. 1 row
B. 3 rows
C. 5 rows
D. 7 rows
7. Which gate is added to the inputs to convert OR gate into NAND gate?
A. XOR
B. AND
C. OR
D. NOT
8. LUT What is the acronym for LUT?
A. Local User Terminal
B. Least Upper Time Period
C. Look Up Table
D. None of given options
9. Final stable state in all cases is ____________.
A. undefined
B. same
C. changed
D. inverted
10. Which gate is equal to the EXCLUSIVE NOR gate if we put the inverter on it?
A. NAND
B. AND
C. XOR
D. OR
11. The three basic gates are
A. NOT, NOR, XOR
B. OR, AND, NAND
C. AND, NAND, XOR
D. NOT, OR, AND
12.In timing problem of _______________ complexity of asynchronous circuit is involved.
A. inputs
B. feedback path
C. clock pulses
D. outputs
MCQs of Digital Logic Design (DLD)
Introduction to Digital Systems
- Analog vs. Digital signals MCQs
- Binary numbers and arithmetic MCQs
- Logic levels and noise margins MCQs
Boolean Algebra
- Basic logic operations (AND, OR, NOT) MCQ
- Laws and theorems of Boolean algebra MCQ
- De Morgan’s Theorems MCQ
- Canonical forms (Sum of Products, Product of Sums) MCQ
- Simplification techniques (Karnaugh Maps, Quine-McCluskey method) MCQ
Combinational Logic
Logic Gates
Combinational Circuits
- Design and analysis of combinational circuits MCQ
- Multiplexers and Demultiplexers MCQ
- Encoders and Decoders MCQ
- Binary Adders (Half adder, Full adder) MCQ
- Subtractors and Arithmetic Logic Units (ALU) MCQ
- Comparators MCQ in DLD
Sequential Logic
Flip-Flops and Latches
- SR Latch, D Latch MCQ
- Flip-Flops (SR, D, JK, T) MCQ
- Characteristic equations and excitation tables MCQ
- Edge-triggered vs. level-triggered devices MCQ
Counters and Registers
- Synchronous, Asynchronous (ripple), Up/Down counters MCQs
- Shift registers (SIPO, PISO, SISO, PIPO) MCQs
State Machines
Finite State Machines (FSMs)
Memory and Programmable Logic MCQs
Memory Devices
- Read-Only Memory (ROM)
- Random Access Memory (RAM)
- Programmable Logic Devices (PLDs) MCQs
- Field Programmable Gate Arrays (FPGAs) MCQs
More MCQs of Digital Logic Design (DLD)
- SET 1: DLD MCQs with answers (dld mcqs with answers)
- SET 2: DLD MCQs (dld basic mcqs)
- SET 3: DLD MCQs (solved mcqs of dld)
- SET 4: DLD MCQs (dld repeated mcqs)
- SET 5: DLD MCQs (dld important mcqs)
- SET 6:DLD MCQs DLD Solved MCQs Answers PDF
MCQs collection of solved and repeated MCQs with answers for the preparation of competitive exams, admission test and job of PPSC, FPSC, UPSC, AP, APPSC, APSC, BPSC, PSC, GOA, GPSC, HPSC, HP, JKPSC, JPSC, KPSC, KERALAPSC, MPPSC, MPSC, MPSCMANIPUR, MPSC, NPSC, OPSC, RPSC, SPSCSKM, TNPSC, TSPSC, TPSC, UPPSC, UKPSC, SPSC, KPPSC, BPSC, AJKPSC ALPSC, NPSC, LPSC, SCPSC, DPSC, DCPSC, PSC, UPSC, WVPSC, PSCW, and WPSC.