SR Latch, D Latch MCQ

By: Prof. Dr. Fazal Rehman | Last updated: June 20, 2025

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1. : What is an SR Latch primarily used for in digital circuits?



2. : What are the two inputs of an SR Latch?



3. : What is the output of an SR Latch if both Set (S) and Reset (R) inputs are LOW (0)?



4. : What happens if both Set (S) and Reset (R) inputs of an SR Latch are HIGH (1)?



5. : Which gate configuration is used to implement an SR Latch?



6. : What is the primary purpose of a D Latch in digital circuits?



7. : What are the two inputs of a D Latch?



8. : What is the output of a D Latch if the Data input is LOW (0) and the Enable input is HIGH (1)?



9. : What is the output of a D Latch if the Data input is HIGH (1) and the Enable input is LOW (0)?



10. : Which gate configuration is used to implement a D Latch?



11. : In an SR Latch, what is the state when both Set (S) and Reset (R) inputs are LOW (0)?



12. : In an SR Latch, what is the state when Set (S) input is HIGH (1) and Reset (R) input is LOW (0)?



13. : In an SR Latch, what is the state when Set (S) input is LOW (0) and Reset (R) input is HIGH (1)?



14. : In an SR Latch, what is the state when both Set (S) and Reset (R) inputs are HIGH (1)?



15. : In a D Latch, what is the state when the Data input is LOW (0) and the Enable input is HIGH (1)?



16. : In a D Latch, what is the state when the Data input is HIGH (1) and the Enable input is LOW (0)?



17. : What is the output of an SR Latch with S=1, R=0 initially, and then S=0, R=0?



18. : What is the output of an SR Latch with S=0, R=1 initially, and then S=0, R=0?



19. : What is the output of a D Latch with D=1 initially, and then D=0?



20. : What is the output of a D Latch with D=0 initially, and then D=1?



 

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