SR Latch, D Latch MCQ

What is an SR Latch primarily used for in digital circuits?

A) To store a single bit of data temporarily
B) To perform arithmetic operations
C) To generate clock signals
D) To convert analog signals to digital
Answer: A
What are the two inputs of an SR Latch?

A) Reset and Hold
B) Set and Reset
C) Clock and Enable
D) Data and Clock
Answer: B
What is the output of an SR Latch if both Set (S) and Reset (R) inputs are LOW (0)?

A) Output HIGH (1)
B) Output LOW (0)
C) Output depends on gate configuration
D) Output cannot be determined
Answer: C
What happens if both Set (S) and Reset (R) inputs of an SR Latch are HIGH (1)?

A) Invalid state, output unpredictable
B) Output remains unchanged
C) Output becomes LOW (0)
D) Output becomes HIGH (1)
Answer: A
Which gate configuration is used to implement an SR Latch?

A) Two cross-coupled NAND gates
B) Two cross-coupled NOR gates
C) One AND gate and one OR gate
D) One XOR gate and one NOT gate
Answer: B
What is the primary purpose of a D Latch in digital circuits?

A) To store a single bit of data temporarily
B) To perform arithmetic operations
C) To generate clock signals
D) To convert analog signals to digital
Answer: A
What are the two inputs of a D Latch?

A) Data and Enable
B) Set and Reset
C) Clock and Data
D) Data and Clock
Answer: A
What is the output of a D Latch if the Data input is LOW (0) and the Enable input is HIGH (1)?

A) Output HIGH (1)
B) Output LOW (0)
C) Output depends on gate configuration
D) Output cannot be determined
Answer: B
What is the output of a D Latch if the Data input is HIGH (1) and the Enable input is LOW (0)?

A) Output HIGH (1)
B) Output LOW (0)
C) Output depends on gate configuration
D) Output cannot be determined
Answer: C
Which gate configuration is used to implement a D Latch?

A) Two cross-coupled NAND gates
B) Two cross-coupled NOR gates
C) One AND gate and one OR gate
D) One XOR gate and one NOT gate
Answer: A
In an SR Latch, what is the state when both Set (S) and Reset (R) inputs are LOW (0)?

A) Set
B) Reset
C) Invalid state
D) Hold
Answer: D
In an SR Latch, what is the state when Set (S) input is HIGH (1) and Reset (R) input is LOW (0)?

A) Set
B) Reset
C) Invalid state
D) Hold
Answer: A
In an SR Latch, what is the state when Set (S) input is LOW (0) and Reset (R) input is HIGH (1)?

A) Set
B) Reset
C) Invalid state
D) Hold
Answer: B
In an SR Latch, what is the state when both Set (S) and Reset (R) inputs are HIGH (1)?

A) Set
B) Reset
C) Invalid state
D) Hold
Answer: C
In a D Latch, what is the state when the Data input is LOW (0) and the Enable input is HIGH (1)?

A) Set
B) Reset
C) Invalid state
D) Hold
Answer: D
In a D Latch, what is the state when the Data input is HIGH (1) and the Enable input is LOW (0)?

A) Set
B) Reset
C) Invalid state
D) Hold
Answer: D
What is the output of an SR Latch with S=1, R=0 initially, and then S=0, R=0?

A) Q = 0, Q’ = 1
B) Q = 1, Q’ = 0
C) Q = 0, Q’ = 0
D) Q = 1, Q’ = 1
Answer: A
What is the output of an SR Latch with S=0, R=1 initially, and then S=0, R=0?

A) Q = 0, Q’ = 1
B) Q = 1, Q’ = 0
C) Q = 0, Q’ = 0
D) Q = 1, Q’ = 1
Answer: B
What is the output of a D Latch with D=1 initially, and then D=0?

A) Q = 0, Q’ = 1
B) Q = 1, Q’ = 0
C) Q = 0, Q’ = 0
D) Q = 1, Q’ = 1
Answer: A
What is the output of a D Latch with D=0 initially, and then D=1?

A) Q = 0, Q’ = 1
B) Q = 1, Q’ = 0
C) Q = 0, Q’ = 0
D) Q = 1, Q’ = 1
Answer: B

MCQs of Digital Logic Design (DLD)

Introduction to Digital Systems

1. Analog vs. Digital signals MCQs
2. Binary numbers and arithmetic MCQs
3. Logic levels and noise margins MCQs

Boolean Algebra

1. Basic logic operations (AND, OR, NOT) MCQ
2. Laws and theorems of Boolean algebra MCQ
3. De Morgan’s Theorems MCQ
4. Canonical forms (Sum of Products, Product of Sums) MCQ
5. Simplification techniques (Karnaugh Maps, Quine-McCluskey method) MCQ

Combinational Logic

Logic Gates

1. Basic gates (AND, OR, NOT) Gat MCQ
2. Universal gates (NAND, NOR) Gat MCQs
3. XOR and XNOR gates MCQ

Combinational Circuits

1. Design and analysis of combinational circuits MCQ
2. Multiplexers and Demultiplexers MCQ
3. Encoders and Decoders MCQ
4. Binary Adders (Half adder, Full adder) MCQ
5. Subtractors and Arithmetic Logic Units (ALU) MCQ
6. Comparators MCQ in DLD

Sequential Logic

Flip-Flops and Latches

1. SR Latch, D Latch MCQ
2. Flip-Flops (SR, D, JK, T) MCQ
3. Characteristic equations and excitation tables MCQ
4. Edge-triggered vs. level-triggered devices MCQ

Counters and Registers

1. Synchronous, Asynchronous (ripple), Up/Down counters MCQs
2. Shift registers (SIPO, PISO, SISO, PIPO) MCQs

State Machines

Finite State Machines (FSMs)

1. Moore and Mealy machines MCQs

Memory and Programmable Logic MCQs

Memory Devices

1. Read-Only Memory (ROM)
2. Random Access Memory (RAM)
3. Programmable Logic Devices (PLDs) MCQs
4. Field Programmable Gate Arrays (FPGAs) MCQs

More MCQs of Digital Logic Design (DLD)

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  • SET 4: DLD MCQs (dld repeated mcqs)
  • SET 5: DLD MCQs (dld important mcqs)
  • SET 6:DLD MCQs DLD Solved MCQs Answers PDF

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