Multiple choice of DLD

By: Prof. Dr. Fazal Rehman | Last updated: April 30, 2025

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1. : __________ is suitable for testing the odd parity of a word.



2. : Due to a change in one input variable, different internal variables change. This makes ____________.



3. : In asynchronous circuits, _____________ is responsible for causing changes.



4. : _________________ will give the sum of full adders as output.



5. : Which of the following inputs overrides the other?



6. : Present state is determined in synchronous circuits by _____________.



7. : How many full and half-adders are required to add a 16-bit number?



8. : __________ is a decade counter.



9. : The present and next states of asynchronous circuits are also known as ____________.



10. : The time required for a pulse to decrease from 90% to 10% of its maximum value is known as ____________.



11. : Where is the logic set when the transmission line is idle in asynchronous transmission?



12. : In ________________, the stable state depends on the order.



 

MCQs of Digital Logic Design (DLD)

Introduction to Digital Systems

  1. Analog vs. Digital signals MCQs
  2. Binary numbers and arithmetic MCQs
  3. Logic levels and noise margins MCQs

Boolean Algebra

  1. Basic logic operations (AND, OR, NOT) MCQ
  2. Laws and theorems of Boolean algebra MCQ
  3. De Morgan’s Theorems MCQ
  4. Canonical forms (Sum of Products, Product of Sums) MCQ
  5. Simplification techniques (Karnaugh Maps, Quine-McCluskey method) MCQ

Combinational Logic

Logic Gates

  1. Basic gates (AND, OR, NOT) Gat MCQ
  2. Universal gates (NAND, NOR) Gat MCQs
  3. XOR and XNOR gates MCQ

Combinational Circuits

  1. Design and analysis of combinational circuits MCQ
  2. Multiplexers and Demultiplexers MCQ
  3. Encoders and Decoders MCQ
  4. Binary Adders (Half adder, Full adder) MCQ
  5. Subtractors and Arithmetic Logic Units (ALU) MCQ
  6. Comparators MCQ in DLD

Sequential Logic

Flip-Flops and Latches

  1. SR Latch, D Latch MCQ
  2. Flip-Flops (SR, D, JK, T) MCQ
  3. Characteristic equations and excitation tables MCQ
  4. Edge-triggered vs. level-triggered devices MCQ

Counters and Registers

  1. Synchronous, Asynchronous (ripple), Up/Down counters MCQs
  2. Shift registers (SIPO, PISO, SISO, PIPO) MCQs

State Machines

Finite State Machines (FSMs)

  1. Moore and Mealy machines MCQs

Memory and Programmable Logic MCQs

Memory Devices

  1. Read-Only Memory (ROM)
  2. Random Access Memory (RAM)
  3. Programmable Logic Devices (PLDs) MCQs
  4. Field Programmable Gate Arrays (FPGAs) MCQs

More MCQs of Digital Logic Design (DLD)

Computer Science Repeated MCQs Book Download

MCQs collection of solved and repeated MCQs with answers for the preparation of competitive exams, admission test and job of PPSC, FPSC, UPSC, AP, APPSC, APSC, BPSC, PSC, GOA, GPSC, HPSC, HP, JKPSC, JPSC, KPSC, KERALAPSC, MPPSC, MPSC, MPSCMANIPUR, MPSC, NPSC, OPSC, RPSC, SPSCSKM, TNPSC, TSPSC, TPSC, UPPSC, UKPSC, SPSC, KPPSC, BPSC, AJKPSC ALPSC, NPSC, LPSC, SCPSC, DPSC, DCPSC, PSC, UPSC, WVPSC, PSCW, and WPSC.

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