ASIC Design and FPGAs MCQs Quizlet (Bank of Solved Questions Answers)
1. What is the inputs in the PLD is given through_______
A. OR gates
B. NAND gates
C. AND gates
D. NOR gates
2. PAL stands for…
A. Programmable Array Logic
B. Programmable Logic Array
C. Programmable Array Loaded
D. None of the these
3. What are the Outputs of AND gate in PLD is said to be _____
A. Both input and output same
B. Strobe lines
C. Output lines
D. Input lines
E. None of the these
4. Which type of PLD should be used, for programmable logic functions?
A. PAL
B. SLD
C. PLA
D. CPLD
5. FPGA device are __________ type.
A. PLD
B. EPROM
C. SROM
D. SLD
6. FPGA stands for…
A. Field Program Gate Array
B. First Program Gate Array
C. Field Programmable Gate Array
D First programmable Gate Array
7. Which of the following full form of VLSI?
A. Very Long Single Integration
B. Very Large Scale Integration
C. Very Least Scale Integration
D. None of the these
8. Vertical and horizontal directions in FPGA are separated by_______
A. A channel
B. A line
C. A flip-flop
D. A strobe
9. Which of the following are applications of PLAs?
A. Configurable PALs
B. Registered PALs
C. FPGA programs
D. All of the these
E. Both A & B
10. The following logic families have the shortest propagation delay…
A. AS-TTL
B. S-TTL
C. HCMOS
D. HS-TTL
11. What is the maximum noise voltage that may appear at the input of a logic gate without changing the logical state of its output is termed as _______
A. Noise Immunity
B. Noise Margin
C. White Noise
D. None of the these
12. What is the Propagation delay?
A. the time taken for the output of a gate to change after the intermediates have changed
B. the time taken for the input of a gate to change after the intermediates have changed
C. the time taken for the input of a gate to change after the outputs have changed
D. the time taken for the output of a gate to change after the inputs have changed