What is TLB? Translation Lookaside Buffer in Paging

What is TLB? Translation Lookaside Buffer in Paging

For the operating system, it is very important to manage the pages. For this purpose operating system creates a page table that contains all the page table entries. Free table entry contains important information about the pages. Some of this important information is  as follows;

  1. The address of the main memory
  2. Important Bits

The address of the main memory

 This address of the main memory is the address where we want to refer.

Important Bits

Page table entry contains the information about the important bits like a dirty bit, protection bit, valid and invalid bits. 

If an operating system wants to search a page from the main memory,  then the operating system simply searches the page from the page table entry.  Page table entry works as a map for locating the pages. 

Where we can store the page table entry?

We can store the page table entry in any of the following;

  1.  Registers
  2.  Cache

Paging with TLB (internal Cache) OR without TLB and with Registers

The page table is located inside the CPU. This can be an internal cache TLB or it can be stored in the registers within the CPU.

  • P is the page number
  • D is the offset: The offset is the base address that is a unique location in the main memory that can serve as a point of reference for other memory locations, commonly called absolute addresses. In order to obtain an absolute address, the offset value is added to the base address.

Paging with TLB (External Cache)

The page table is located outside the CPU. This can be an external cache commonly called TLB and this external cache is not located inside the CPU.

TLB Translation Lookaside Buffer with External Cache in Paging
Figure: TLB Translation Lookaside Buffer with External Cache in Paging

Advantages of storing the page table entry in the registers?

The speed of registers is very fast. If CPU wants to get the page table Entry from the registers,  then resistors can provide the page table entry with good speed.

The disadvantage of storing the page table entry in the registers?

The size of the registers is very small and it is very difficult to manage the big processes in the small registers.

Advantage of storing the page table entry in the Cache?

The cache is big in size as compared to the registers, so the cache can handle big processes page table entries.

Disadvantages of storing the page table entry in the Cache?

If CPU wants to access the page table Entry from the cache,  then the speed of the cache is slow as compared to the registers.

What is the better way to store the page table entries?

The size of the register is very small so it is not a good approach to store the Page table entry in registers. So it is better to store the page table entry in the cache. 

What is the translation lookaside buffer (TLB)?

The cache used to store the page table entries is commonly called translation lookaside buffer. 

TLB  is just a special kind of cache used to maintain the records of recently used transactions. TLB contains the page table entries that have been most recently used by the operating system and CPU.

What is TLB hit and TLB Miss?

If CPU requires a page table entry and the page table entry is present in the TLB, then it is called TLB hit.

If CPU requires a page table entry and the page table entry is not present in the TLB, then it is called TLB miss.

What is the page number?

A page number is a specific number that is assigned to each page and it is used to indicate the process page table.

Steps for the demonstration of a TLB hit

First of all, the CPU generates a virtual address.

The checking of the address is done in TLB. 

Display the corresponding frame number. This frame number tells the CPU where the page is located in the main memory.

What is Effective memory access time(EMAT)?

TLB is used to reduce effective memory access time by using the concept of the cache.

Effective memory acess time can be calculated with the help of the following formula;

EMAT = h*(c+m) + (1-h)*(c+2m) 

where, h = hit ratio of TLB

m = Memory access time

c = TLB access time

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