Pipeline Hazards MCQs

By: Prof. Dr. Fazal Rehman Shamil | Last updated: September 20, 2024

What type of pipeline hazard occurs when two instructions need the same resource?
A) Data Hazard
B) Structural Hazard
C) Control Hazard
D) Resource Hazard
Answer: B

Which hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed?
A) Data Hazard
B) Structural Hazard
C) Control Hazard
D) Resource Hazard
Answer: A

What is the primary solution for structural hazards in pipelined processors?
A) Stalling
B) Resource Duplication
C) Branch Prediction
D) Out-of-Order Execution
Answer: B

Which type of hazard arises from a branch instruction that changes the flow of control?
A) Data Hazard
B) Structural Hazard
C) Control Hazard
D) Resource Hazard
Answer: C

What technique is commonly used to handle data hazards in pipelined processors?
A) Branch Prediction
B) Register Renaming
C) Resource Duplication
D) Speculative Execution
Answer: B

In a pipeline, what is the effect of a structural hazard?
A) It causes incorrect results due to delayed data
B) It creates a conflict for hardware resources
C) It leads to incorrect branch outcomes
D) It results in data forwarding
Answer: B

Which hazard can be mitigated by using branch prediction techniques?
A) Data Hazard
B) Structural Hazard
C) Control Hazard
D) Resource Hazard
Answer: C

What is the purpose of data forwarding in a pipelined processor?
A) To eliminate control hazards
B) To resolve conflicts over hardware resources
C) To pass data directly between pipeline stages
D) To predict branch outcomes
Answer: C

Which hazard occurs when an instruction must wait for data from a previous instruction?
A) Structural Hazard
B) Control Hazard
C) Data Hazard
D) Resource Hazard
Answer: C

What solution is used to manage control hazards in pipelined processors?
A) Data Forwarding
B) Branch Prediction
C) Resource Duplication
D) Register Renaming
Answer: B

What is the main issue caused by structural hazards?
A) Execution delays due to waiting for data
B) Incorrect results from uncompleted instructions
C) Conflicts over the use of hardware resources
D) Mis-speculated branch outcomes
Answer: C

Which of the following techniques helps to reduce the impact of data hazards?
A) Stalling
B) Branch Prediction
C) Resource Duplication
D) Speculative Execution
Answer: A

What is an example of a data hazard that can be resolved by data forwarding?
A) RAW (Read After Write) Hazard
B) WAR (Write After Read) Hazard
C) WAW (Write After Write) Hazard
D) Structural Hazard
Answer: A

Which type of hazard can be minimized by implementing out-of-order execution?
A) Structural Hazard
B) Data Hazard
C) Control Hazard
D) Resource Hazard
Answer: B

What kind of hazard is addressed by adding more functional units in a processor?
A) Data Hazard
B) Control Hazard
C) Structural Hazard
D) Resource Hazard
Answer: C

Which hazard occurs when two instructions write to the same register in a pipeline?
A) RAW Hazard
B) WAR Hazard
C) WAW Hazard
D) Structural Hazard
Answer: C

What is the primary purpose of branch prediction in pipelined processors?
A) To avoid data hazards
B) To reduce structural hazards
C) To improve control flow performance
D) To eliminate resource conflicts
Answer: C

What technique can be used to handle a Write-After-Read (WAR) hazard?
A) Data Forwarding
B) Register Renaming
C) Branch Prediction
D) Resource Duplication
Answer: B

Which of the following is a consequence of a control hazard in pipelined execution?
A) Incorrect data being used
B) Hardware resource conflicts
C) Pipeline stalls or bubbles
D) Incorrect branch predictions
Answer: C

What is the purpose of pipeline stalling in the context of data hazards?
A) To allow instructions to proceed without interference
B) To wait until the data dependency is resolved
C) To eliminate control hazards
D) To handle structural conflicts
Answer: B

Which type of hazard can be resolved using register renaming?
A) Data Hazard
B) Structural Hazard
C) Control Hazard
D) Resource Hazard
Answer: A

How does speculative execution help manage pipeline hazards?
A) By reducing structural conflicts
B) By predicting and executing potential future instructions
C) By forwarding data between pipeline stages
D) By handling control hazards directly
Answer: B

What happens when a branch instruction is mis-predicted?
A) The pipeline continues without interruption
B) The processor performs extra work that must be discarded
C) The pipeline stalls until the correct branch is resolved
D) Data forwarding corrects the mis-prediction
Answer: B

Which pipeline hazard occurs when instructions are executed out of order but need results from previous instructions?
A) Data Hazard
B) Control Hazard
C) Structural Hazard
D) Resource Hazard
Answer: A

What is the primary issue with a Write-After-Write (WAW) hazard?
A) Incorrect data read due to a write delay
B) Multiple instructions writing to the same register
C) Conflicts over the usage of functional units
D) Branch mis-predictions affecting execution
Answer: B

What is the purpose of a branch target buffer (BTB) in branch prediction?
A) To store recent data values
B) To keep track of recently executed branches
C) To forward data between pipeline stages
D) To resolve structural hazards
Answer: B

Which technique involves delaying the execution of an instruction to avoid conflicts with previous instructions?
A) Data Forwarding
B) Pipeline Stalling
C) Out-of-Order Execution
D) Branch Prediction
Answer: B

What is the role of instruction reordering in managing pipeline hazards?
A) To resolve control hazards
B) To handle data dependencies by changing instruction sequence
C) To duplicate hardware resources
D) To handle resource conflicts
Answer: B

Which type of hazard is least affected by the addition of more functional units?
A) Data Hazard
B) Structural Hazard
C) Control Hazard
D) Resource Hazard
Answer: C

How does register renaming prevent Write-After-Write (WAW) hazards?
A) By avoiding conflicts with data forwarding
B) By providing unique register identifiers to instructions
C) By predicting branch outcomes more accurately
D) By duplicating hardware resources
Answer: B

What happens during a pipeline stall?
A) Instructions are executed out of order
B) The pipeline holds up the execution of subsequent instructions
C) Data is forwarded between stages
D) Branch prediction is re-evaluated
Answer: B

What is the goal of speculative execution in pipeline processing?
A) To reduce the number of pipeline stages
B) To execute instructions before knowing the outcome of a branch
C) To resolve structural hazards
D) To handle data hazards through forwarding
Answer: B

What technique can be used to address Write-After-Read (WAR) hazards?
A) Pipeline Stalling
B) Data Forwarding
C) Register Renaming
D) Branch Prediction
Answer: C

What is the effect of a mis-predicted branch on pipeline performance?
A) It improves performance by reducing stalls
B) It leads to pipeline flushing and re-execution of instructions
C) It resolves data hazards
D) It minimizes structural conflicts
Answer: B

What is the primary benefit of implementing multiple functional units in a processor?
A) To handle data hazards
B) To manage control hazards
C) To avoid structural hazards
D) To predict branch outcomes
Answer: C

Which hazard is directly addressed by adding more registers?
A) Data Hazard
B) Structural Hazard
C) Control Hazard
D) Resource Hazard
Answer: A

What type of pipeline hazard occurs when a functional unit is over-utilized?
A) Data Hazard
B) Control Hazard
C) Structural Hazard
D) Resource Hazard
Answer: C

Which technique helps to minimize the impact of control hazards?
A) Data Forwarding
B) Resource Duplication
C) Branch Prediction
D) Register Renaming
Answer: C

What does out-of-order execution aim to resolve in pipelined processors?
A) Structural Hazards
B) Data Hazards
C) Control Hazards
D) Resource Hazards
Answer: B

What is the primary challenge of a branch mis-prediction in pipelined execution?
A) Incorrect results due to data dependencies
B) Pipeline flushing and re-execution
C) Resource conflicts leading to stalls
D) Incorrect execution due to functional unit delays
Answer: B

What is the role of a reservation station in a pipelined processor?
A) To manage control flow and branch prediction
B) To handle instruction dependencies and data forwarding
C) To prevent structural hazards by duplicating resources
D) To perform speculative execution
Answer: B

How does branch prediction affect the efficiency of pipelined processors?
A) It increases the number of pipeline stages
B) It reduces the need for data forwarding
C) It decreases the likelihood of pipeline stalls
D) It resolves Write-After-Write hazards
Answer: C

Which hazard can be mitigated by increasing the number of pipeline stages?
A) Data Hazard
B) Control Hazard
C) Structural Hazard
D) Resource Hazard
Answer: C

What is a primary strategy to handle a Read-After-Write (RAW) hazard?
A) Using data forwarding
B) Adding more registers
C) Increasing pipeline depth
D) Implementing branch prediction
Answer: A

Which hazard can occur if an instruction writes to a register that is being read by a subsequent instruction?
A) Write-After-Read (WAR) Hazard
B) Read-After-Write (RAW) Hazard
C) Write-After-Write (WAW) Hazard
D) Control Hazard
Answer: B

What type of hazard can be managed by reordering instructions in a pipeline?
A) Data Hazard
B) Control Hazard
C) Structural Hazard
D) Resource Hazard
Answer: A

Which pipeline technique can help alleviate the penalties associated with branch mis-prediction?
A) Branch Prediction
B) Data Forwarding
C) Out-of-Order Execution
D) Resource Duplication
Answer: A

What is a common technique to resolve a Write-After-Read (WAR) hazard?
A) Using additional pipeline stages
B) Register Renaming
C) Branch Prediction
D) Resource Duplication
Answer: B

What type of hazard does adding more execution units in a processor primarily address?
A) Data Hazard
B) Control Hazard
C) Structural Hazard
D) Resource Hazard
Answer: C

Which hazard involves a situation where an instruction needs to use a functional unit that is already in use?
A) Data Hazard
B) Control Hazard
C) Structural Hazard
D) Resource Hazard
Answer: C

What method is used to avoid pipeline stalls due to data hazards?
A) Data Forwarding
B) Branch Prediction
C) Out-of-Order Execution
D) Resource Duplication
Answer: A

Read More Computer Architecture MCQs

1. SET 1: Computer Architecture MCQs
2. SET 2: Computer Architecture MCQs
3. SET 3: Computer Architecture MCQs
4. SET 4: Computer Architecture MCQs
5. SET 5: Computer Architecture MCQs
6. SET 6: Computer Architecture MCQs
7. SET 7: Computer Architecture MCQs
8. SET 8: Computer Architecture MCQs
9. SET 9: Computer Architecture MCQs

• Introduction to Computer Architecture MCQs
  • Evolution of Computer Architecture MCQs
  • von Neumann vs Harvard Architecture MCQs
• Basic Components of a Computer System MCQs
  • Central Processing Unit (CPU) MCQs
  • Memory (RAM, ROM, Cache) MCQs
  • Input/Output (I/O) Devices MCQs
  • Buses (Data, Address, Control) MCQs
• CPU Organization MCQs
  • ALU (Arithmetic Logic Unit) MCQs
  • Control Unit MCQs
  • Registers (General Purpose, Special Purpose) MCQs
  • Flags and Status Registers MCQs
• Instruction Set Architecture (ISA) MCQs
  • Types of Instructions (Data Movement, Arithmetic, Control) MCQs
  • Addressing Modes (Immediate, Direct, Indirect, Indexed) MCQs
  • Instruction Formats MCQs
  • RISC (Reduced Instruction Set Computer) vs CISC (Complex Instruction Set Computer) MCQs
• Microarchitecture MCQs
  • Pipelining (Stages and Hazards) MCQs
  • Superscalar Architecture MCQs
  • Multithreading MCQs
  • Out-of-Order Execution MCQs
• Memory Hierarchy MCQs
  • Cache Memory (L1, L2, L3) MCQs
  • Virtual Memory MCQs
  • Paging and Segmentation MCQs
  • TLB (Translation Lookaside Buffer) MCQs
• Cache Memory MCQs
  • Cache Mapping Techniques (Direct, Associative, Set-Associative) MCQs
  • Cache Coherency MCQs
  • Write Policies (Write-Through, Write-Back) MCQs
  • Cache Miss and Hit MCQs
• Input/Output Organization MCQs
  • I/O Techniques (Polling, Interrupts, DMA) MCQs
  • I/O Mapping (Memory-Mapped I/O, Isolated I/O) MCQs
  • Interrupt Handling MCQs
• Bus Architecture MCQs
  • System Bus (Data, Address, Control) MCQs
  • Bus Arbitration MCQs
  • Synchronous vs Asynchronous Buses MCQs
• Performance Metrics MCQs
  • Clock Speed and Cycles per Instruction (CPI) MCQs
  • MIPS (Million Instructions per Second) MCQs
  • FLOPS (Floating-Point Operations per Second) MCQs
  • Amdahl’s Law MCQs
• Parallelism in Computer Architecture MCQs
  • Instruction-Level Parallelism (ILP) MCQs
  • Data-Level Parallelism (DLP) MCQs
  • Thread-Level Parallelism (TLP) MCQs
  • Symmetric Multiprocessing (SMP) vs Asymmetric Multiprocessing (AMP) MCQs
• Multicore and Multiprocessor Systems MCQs
  • Multicore Architectures MCQs
  • Shared Memory vs Distributed Memory MCQs
  • Interconnection Networks MCQs
• Control Unit Design MCQs
  • Hardwired Control vs Microprogrammed Control MCQs
  • Control Signals and Timing MCQs
  • Instruction Cycle and Control Flow MCQs
• Pipeline Hazards MCQs
  • Structural, Data, and Control Hazards MCQs
  • Techniques to Overcome Hazards (Stalling, Forwarding, Branch Prediction) MCQs
• Branch Prediction and Speculation MCQs
  • Static and Dynamic Branch Prediction MCQs
  • Speculative Execution MCQs
  • Branch Target Buffers MCQs
• Arithmetic and Logic Operations MCQs
  • Integer and Floating-Point Arithmetic MCQs
  • ALU Design MCQs
  • Fixed-Point vs Floating-Point Representation MCQs
• Memory Management MCQs
  • Paging, Segmentation, and Virtual Memory MCQs
  • Memory Protection and Privilege Levels MCQs
  • Memory Allocation and Deallocation MCQs
• Power and Energy Efficiency MCQs
  • Power Dissipation in CPUs MCQs
  • Low-Power Design Techniques MCQs
  • Energy-Aware Computing MCQs
• Advanced Topics MCQs
  • GPU Architecture and Usage MCQs
  • Quantum Computing Basics MCQs
  • Neuromorphic Computing MCQs
• Emerging Trends
  • Cloud Computing Architectures MCQs
  • Edge Computing MCQs
  • AI Accelerators MCQs