Computer Architecture Test MCQs

By: Prof. Dr. Fazal Rehman | Last updated: September 20, 2024

Computer Architecture Test MCQs

1. What is the main virtue for using single Bus structure?
A. Cost effective connectivity and ease of attaching peripheral devices
B. Fast data transfers
C. Cost effective connectivity and speed
D. None of these

2. __________ is the advantage of a single bus over a multibus:
A. High operating speed
B. Flexibility in attaching peripheral devices
C. Low cost
D. Both B & C

3. In various devices,________ are used to overcome the difference in data transfer speed:
A. Multiple Buses
B. Buffer registers
C. Speed-enhancing circuitry
D. Bridge circuits

4. Why is an extra clock needed in serial communication?
A. To make efficient use of RS-232
B. To synchronize the devices
C. For programmed baud rate control
D. None of these

5. What do we use to extend the connectivity of the processor bus?
A. PCI bus
B. Multiple bus
C. SCSI bus
D. Controllers

6. The idle situation occurs in which of the following instruction bus?
A. INX H
B. DAA
C. EI
D. DAD RP

7. What does a bus standard developed by IBM for their line of computers ‘PC AT’ called?
A. M-bus
B. ISA
C. IB bus
D. None of these

8. What is the addressing called that is used in an instruction of the form ADD X Y is?
A. Indirect
B. Index
C. Absolute
D. Immediate

9. _______ is the bus used to connect the monitor to the CPU:
A. Memory bus
B. Rambus
C. PCI bus
D. SCSI bus

10. Through which technique, the speed imbalance between memory access and CPU operation can be reduced?
A. Memory interleaving
B. Cache memory
C. Reducing the size of memory
D. Both A & B

11. What does ANSI stand for?
A. American National Standards Institute
B. American Network Standard Interfacing
C. American Network Security Interrupt
D. American National Standard Interface

12. _______ does not need extra hardware for refreshing of DRAM:
A. Motorola – 6800
B. 8085
C. Z – 80
D. All of these

 

Read More Computer Architecture MCQs

1. SET 1: Computer Architecture MCQs
2. SET 2: Computer Architecture MCQs
3. SET 3: Computer Architecture MCQs
4. SET 4: Computer Architecture MCQs
5. SET 5: Computer Architecture MCQs
6. SET 6: Computer Architecture MCQs
7. SET 7: Computer Architecture MCQs
8. SET 8: Computer Architecture MCQs
9. SET 9: Computer Architecture MCQs

• Introduction to Computer Architecture MCQs
  • Evolution of Computer Architecture MCQs
  • von Neumann vs Harvard Architecture MCQs
• Basic Components of a Computer System MCQs
  • Central Processing Unit (CPU) MCQs
  • Memory (RAM, ROM, Cache) MCQs
  • Input/Output (I/O) Devices MCQs
  • Buses (Data, Address, Control) MCQs
• CPU Organization MCQs
  • ALU (Arithmetic Logic Unit) MCQs
  • Control Unit MCQs
  • Registers (General Purpose, Special Purpose) MCQs
  • Flags and Status Registers MCQs
• Instruction Set Architecture (ISA) MCQs
  • Types of Instructions (Data Movement, Arithmetic, Control) MCQs
  • Addressing Modes (Immediate, Direct, Indirect, Indexed) MCQs
  • Instruction Formats MCQs
  • RISC (Reduced Instruction Set Computer) vs CISC (Complex Instruction Set Computer) MCQs
• Microarchitecture MCQs
  • Pipelining (Stages and Hazards) MCQs
  • Superscalar Architecture MCQs
  • Multithreading MCQs
  • Out-of-Order Execution MCQs
• Memory Hierarchy MCQs
  • Cache Memory (L1, L2, L3) MCQs
  • Virtual Memory MCQs
  • Paging and Segmentation MCQs
  • TLB (Translation Lookaside Buffer) MCQs
• Cache Memory MCQs
  • Cache Mapping Techniques (Direct, Associative, Set-Associative) MCQs
  • Cache Coherency MCQs
  • Write Policies (Write-Through, Write-Back) MCQs
  • Cache Miss and Hit MCQs
• Input/Output Organization MCQs
  • I/O Techniques (Polling, Interrupts, DMA) MCQs
  • I/O Mapping (Memory-Mapped I/O, Isolated I/O) MCQs
  • Interrupt Handling MCQs
• Bus Architecture MCQs
  • System Bus (Data, Address, Control) MCQs
  • Bus Arbitration MCQs
  • Synchronous vs Asynchronous Buses MCQs
• Performance Metrics MCQs
  • Clock Speed and Cycles per Instruction (CPI) MCQs
  • MIPS (Million Instructions per Second) MCQs
  • FLOPS (Floating-Point Operations per Second) MCQs
  • Amdahl’s Law MCQs
• Parallelism in Computer Architecture MCQs
  • Instruction-Level Parallelism (ILP) MCQs
  • Data-Level Parallelism (DLP) MCQs
  • Thread-Level Parallelism (TLP) MCQs
  • Symmetric Multiprocessing (SMP) vs Asymmetric Multiprocessing (AMP) MCQs
• Multicore and Multiprocessor Systems MCQs
  • Multicore Architectures MCQs
  • Shared Memory vs Distributed Memory MCQs
  • Interconnection Networks MCQs
• Control Unit Design MCQs
  • Hardwired Control vs Microprogrammed Control MCQs
  • Control Signals and Timing MCQs
  • Instruction Cycle and Control Flow MCQs
• Pipeline Hazards MCQs
  • Structural, Data, and Control Hazards MCQs
  • Techniques to Overcome Hazards (Stalling, Forwarding, Branch Prediction) MCQs
• Branch Prediction and Speculation MCQs
  • Static and Dynamic Branch Prediction MCQs
  • Speculative Execution MCQs
  • Branch Target Buffers MCQs
• Arithmetic and Logic Operations MCQs
  • Integer and Floating-Point Arithmetic MCQs
  • ALU Design MCQs
  • Fixed-Point vs Floating-Point Representation MCQs
• Memory Management MCQs
  • Paging, Segmentation, and Virtual Memory MCQs
  • Memory Protection and Privilege Levels MCQs
  • Memory Allocation and Deallocation MCQs
• Power and Energy Efficiency MCQs
  • Power Dissipation in CPUs MCQs
  • Low-Power Design Techniques MCQs
  • Energy-Aware Computing MCQs
• Advanced Topics MCQs
  • GPU Architecture and Usage MCQs
  • Quantum Computing Basics MCQs
  • Neuromorphic Computing MCQs
• Emerging Trends
  • Cloud Computing Architectures MCQs
  • Edge Computing MCQs
  • AI Accelerators MCQs