Microarchitecture MCQs – T4Tutorials.com

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1. : What is microarchitecture?
(A) High-level program design
(B) The hardware that implements instruction execution
(C) The software controlling hardware
(D) Data transfer between registers

2. : What is the main function of the Control Unit in a CPU?
(A) Perform calculations
(B) Control the flow of instructions
(C) Store data
(D) Access memory

3. : Which microarchitectural component is responsible for performing arithmetic operations?
(A) Control Unit
(B) ALU
(C) Cache
(D) Decoder

4. : Which of the following is a type of microarchitecture pipeline stage?
(A) Decode
(B) Fetch
(C) Write-back
(D) All of the above

5. : What is instruction pipelining in microarchitecture?
(A) Executing multiple instructions simultaneously
(B) Splitting an instruction into smaller steps processed in parallel
(C) Decoding instructions at runtime
(D) Fetching data from memory

6. : Which of the following is a hazard in pipelined microarchitecture?
(A) Data hazard
(B) Control hazard
(C) Structural hazard
(D) All of the above

7. : What is branch prediction used for in microarchitectures?
(A) To speed up arithmetic operations
(B) To minimize pipeline stalls
(C) To decode instructions faster
(D) To handle memory access

8. : What is a superscalar architecture?
(A) An architecture that executes one instruction at a time
(B) An architecture that can execute multiple instructions per clock cycle
(C) An architecture without any cache
(D) An architecture that only uses one pipeline

9. : Which cache is closest to the CPU in a typical microarchitecture?
(A) L1 cache
(B) L2 cache
(C) L3 cache
(D) Main memory

10. : What is out-of-order execution?
(A) Executing instructions in the exact order they arrive
(B) Executing instructions based on data availability and resources
(C) Fetching data randomly from memory
(D) Running instructions serially

11. : Which component in microarchitecture handles memory read and write operations?
(A) ALU
(B) Memory Management Unit (MMU)
(C) Control Unit
(D) Decoder

12. : What is register renaming used for in modern CPUs?
(A) To prevent register conflicts
(B) To speed up memory access
(C) To increase register size
(D) To minimize cache misses

13. : What is a pipeline stall?
(A) When the pipeline has no instructions to process
(B) When multiple instructions are executed simultaneously
(C) When the CPU runs out of power
(D) When a pipeline stage must wait for data or resources

14. : What does ILP stand for in microarchitecture?
(A) Instruction Load Processing
(B) Instruction Level Parallelism
(C) Independent Logical Processing
(D) Interlocked Processing

15. : How does speculative execution improve performance?
(A) By executing instructions without dependencies
(B) By guessing the outcome of branches and executing ahead
(C) By caching all instructions in advance
(D) By improving the fetch rate

16. : Which technique is used to handle data hazards in pipelined processors?
(A) Instruction reordering
(B) Register renaming
(C) Bypassing/Forwarding
(D) Instruction caching

17. : What is the purpose of a reorder buffer (ROB)?
(A) To fetch instructions
(B) To retire instructions in the correct order
(C) To decode multiple instructions
(D) To store intermediate arithmetic results

18. : What is micro-op fusion?
(A) Combining multiple micro-operations into a single instruction
(B) Splitting one instruction into multiple micro-operations
(C) Merging pipeline stages
(D) Reducing instruction size

19. : What is the role of a prefetcher in a CPU?
(A) To decode instructions
(B) To fetch data or instructions from memory ahead of time
(C) To execute speculative instructions
(D) To write back results to memory

20. : Which microarchitecture feature helps handle control hazards?
(A) Bypassing
(B) Branch prediction
(C) Cache coherence
(D) Pipeline flush

21. : What is the main goal of microarchitectural optimizations?
(A) Increase energy consumption
(B) Improve instruction throughput and efficiency
(C) Slow down execution for better debugging
(D) Simplify the hardware design

22. : What does VLIW stand for?
(A) Variable Length Instruction Word
(B) Very Large Instruction Word
(C) Vector Load Instruction Word
(D) Virtual Logical Instruction Width

23. : What is a cache miss?
(A) When data is found in the cache
(B) When the CPU cannot access the cache
(C) When requested data is not found in the cache
(D) When the cache is full

24. : What is the role of a decoder in CPU microarchitecture?
(A) To perform arithmetic calculations
(B) To convert instructions into control signals
(C) To manage memory allocation
(D) To store instructions

25. : What is a structural hazard in pipelining?
(A) When two instructions require the same hardware resource
(B) When there is a data dependency between instructions
(C) When the instruction decoder fails
(D) When cache memory fails to respond

26. : What is hyper-threading in CPU architecture?
(A) Executing multiple threads per core
(B) Improving clock speed
(C) Creating larger caches
(D) Using multiple pipelines for a single thread

27. : What does speculative execution require to function properly?
(A) Register renaming
(B) Branch prediction
(C) Cache coherence
(D) ALU pipelining

28. : What does CISC stand for in microarchitecture?
(A) Complex Instruction Set Computing
(B) Cyclic Instruction Set Computing
(C) Cache Independent System Core
(D) Clustered Instruction System Computing

29. : What is meant by a ‘cache hit’?
(A) The CPU fails to find data in cache
(B) Data is successfully retrieved from the cache
(C) Cache memory overflows
(D) Cache memory is cleared

30. : How does out-of-order execution impact CPU performance?
(A) It reduces performance by delaying instructions
(B) It enhances performance by optimizing instruction execution
(C) It slows down memory access
(D) It leads to increased energy consumption

31. : What is the function of a write-back stage in a pipeline?
(A) Decode instructions
(B) Execute instructions
(C) Write the result back to memory
(D) Fetch data

32. : In modern microarchitectures, what is the role of a load/store unit?
(A) Execute arithmetic instructions
(B) Perform data memory access operations
(C) Control the flow of instructions
(D) Manage branch prediction

33. : What is a control hazard also known as?
(A) Branch hazard
(B) Cache hazard
(C) Data hazard
(D) ALU hazard

34. : What is instruction-level parallelism (ILP) in microarchitecture?
(A) The execution of instructions one at a time
(B) The execution of multiple instructions in parallel within a CPU
(C) The reordering of instructions for better performance
(D) The decoding of multiple instructions simultaneously

35. : Which technique is used to improve cache performance?
(A) Pipelining
(B) Caching algorithms
(C) Cache prefetching
(D) Branch prediction

36. : What does the term ‘pipeline flush’ refer to in CPU microarchitecture?
(A) Clearing out stalled pipeline stages
(B) Adding more stages to the pipeline
(C) Prefetching instructions
(D) Storing intermediate results in the cache

37. : What type of microarchitecture hazard occurs when a resource is not available for an instruction?
(A) Control hazard
(B) Data hazard
(C) Structural hazard
(D) Branch hazard

38. : What is meant by ‘superscalar’ execution?
(A) Using multiple threads on a single core
(B) Executing more than one instruction per clock cycle
(C) Running instructions in a serial order
(D) Reducing instruction sizes for better performance

39. : What is the key feature of a Reduced Instruction Set Computing (RISC) architecture?
(A) It uses complex instructions
(B) It executes instructions in parallel
(C) It has a large instruction set
(D) It uses simple instructions executed quickly

40. : In a pipelined processor, what does the term ‘bypassing’ refer to?
(A) Skipping instruction execution
(B) Forwarding data between pipeline stages to avoid stalls
(C) Flushing the pipeline after every instruction
(D) Reducing the number of instructions fetched

41. : Which of the following techniques helps in minimizing cache misses?
(A) Cache blocking
(B) Instruction pipelining
(C) Branch prediction
(D) Register renaming

42. : What is a vector processor in microarchitecture?
(A) A processor that handles scalar operations
(B) A processor that operates on one element at a time
(C) A processor that operates on entire arrays of data
(D) A processor that manages only floating-point operations

43. : What is the function of an instruction queue in microarchitecture?
(A) Store arithmetic results
(B) Hold instructions before they are executed
(C) Prefetch memory data
(D) Cache recently executed instructions

44. : What does the acronym MMU stand for in CPU microarchitecture?
(A) Microcode Memory Unit
(B) Memory Management Unit
(C) Machine Microprocessor Unit
(D) Macro Memory Unit

45. : What is meant by ‘multi-threading’ in CPU microarchitecture?
(A) Executing multiple instructions in parallel
(B) Running multiple threads on a single processor core
(C) Fetching multiple instructions simultaneously
(D) Storing instructions in different registers

46. : What is instruction reordering used for in microarchitecture?
(A) To improve cache performance
(B) To avoid pipeline stalls and hazards
(C) To execute instructions out of order for faster execution
(D) To prevent branch mispredictions

47. : What does SIMD stand for in microarchitectures?
(A) Single Instruction Multiple Data
(B) Single Instruction Multiple Decode
(C) Serial Instruction Memory Data
(D) Scalar Integer Micro Data

48. : What is the purpose of dynamic scheduling in CPUs?
(A) To improve speculative execution
(B) To allow out-of-order execution based on resource availability
(C) To reduce clock speed
(D) To synchronize threads

49. : What is a core in the context of microarchitecture?
(A) The instruction decoder of the CPU
(B) A single processing unit within the CPU
(C) The memory management unit of the CPU
(D) The ALU of the CPU

50. : What is the main advantage of branch prediction?
(A) It speeds up instruction decoding
(B) It reduces the number of pipeline stalls caused by branch instructions
(C) It prevents cache misses
(D) It eliminates the need for speculative execution

Microarchitecture MCQs
By: Prof. Dr. Fazal Rehman | Last updated: June 23, 2025

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