Branch Target Buffers MCQs 5 Score: 0 Attempted: 0/5 1. The Branch Target Buffer (BTB) is used to: (A) Store predicted branch outcomes (B) Store target addresses of taken branches (C) Store the branch instruction itself (D) Store the pipeline status during a branch 2. BTB is typically implemented in: (A) Data cache (B) Instruction cache (C) CPU registers (D) Separate hardware unit 3. The purpose of a Branch Target Buffer is to: (A) Predict branch direction (B) Store past instruction results (C) Cache memory addresses (D) Store target addresses for predicted taken branches 4. A BTB miss occurs when: (A) The predicted branch is not taken (B) The predicted branch outcome is wrong (C) The branch target is not found in the BTB (D) The pipeline is stalled 5. BTB stores information about: (A) The next instruction to be executed (B) The target address of taken branches (C) The register file state (D) Cache misses and hits Read More Computer Architecture MCQs SET 1: Computer Architecture MCQs SET 2: Computer Architecture MCQs SET 3: Computer Architecture MCQs SET 4: Computer Architecture MCQs SET 5: Computer Architecture MCQs SET 6: Computer Architecture MCQs SET 7: Computer Architecture MCQs SET 8: Computer Architecture MCQs SET 9: Computer Architecture MCQs Introduction to Computer Architecture MCQs Evolution of Computer Architecture MCQs von Neumann vs Harvard Architecture MCQs Basic Components of a Computer System MCQs Central Processing Unit (CPU) MCQs Memory (RAM, ROM, Cache) MCQs Input/Output (I/O) Devices MCQs Buses (Data, Address, Control) MCQs CPU Organization MCQs ALU (Arithmetic Logic Unit) MCQs Control Unit MCQs Registers (General Purpose, Special Purpose) MCQs Flags and Status Registers MCQs Instruction Set Architecture (ISA) MCQs Types of Instructions (Data Movement, Arithmetic, Control) MCQs Addressing Modes (Immediate, Direct, Indirect, Indexed) MCQs Instruction Formats MCQs RISC (Reduced Instruction Set Computer) vs CISC (Complex Instruction Set Computer) MCQs Microarchitecture MCQs Pipelining (Stages and Hazards) MCQs Superscalar Architecture MCQs Multithreading MCQs Out-of-Order Execution MCQs Memory Hierarchy MCQs Cache Memory (L1, L2, L3) MCQs Virtual Memory MCQs Paging and Segmentation MCQs TLB (Translation Lookaside Buffer) MCQs Cache Memory MCQs Cache Mapping Techniques (Direct, Associative, Set-Associative) MCQs Cache Coherency MCQs Write Policies (Write-Through, Write-Back) MCQs Cache Miss and Hit MCQs Input/Output Organization MCQs I/O Techniques (Polling, Interrupts, DMA) MCQs I/O Mapping (Memory-Mapped I/O, Isolated I/O) MCQs Interrupt Handling MCQs Bus Architecture MCQs System Bus (Data, Address, Control) MCQs Bus Arbitration MCQs Synchronous vs Asynchronous Buses MCQs Performance Metrics MCQs Clock Speed and Cycles per Instruction (CPI) MCQs MIPS (Million Instructions per Second) MCQs FLOPS (Floating-Point Operations per Second) MCQs Amdahl’s Law MCQs Parallelism in Computer Architecture MCQs Instruction-Level Parallelism (ILP) MCQs Data-Level Parallelism (DLP) MCQs Thread-Level Parallelism (TLP) MCQs Symmetric Multiprocessing (SMP) vs Asymmetric Multiprocessing (AMP) MCQs Multicore and Multiprocessor Systems MCQs Multicore Architectures MCQs Shared Memory vs Distributed Memory MCQs Interconnection Networks MCQs Control Unit Design MCQs Hardwired Control vs Microprogrammed Control MCQs Control Signals and Timing MCQs Instruction Cycle and Control Flow MCQs Pipeline Hazards MCQs Structural, Data, and Control Hazards MCQs Techniques to Overcome Hazards (Stalling, Forwarding, Branch Prediction) MCQs Branch Prediction and Speculation MCQs Static and Dynamic Branch Prediction MCQs Speculative Execution MCQs Branch Target Buffers MCQs Arithmetic and Logic Operations MCQs Integer and Floating-Point Arithmetic MCQs ALU Design MCQs Fixed-Point vs Floating-Point Representation MCQs Memory Management MCQs Paging, Segmentation, and Virtual Memory MCQs Memory Protection and Privilege Levels MCQs Memory Allocation and Deallocation MCQs Power and Energy Efficiency MCQs Power Dissipation in CPUs MCQs Low-Power Design Techniques MCQs Energy-Aware Computing MCQs Advanced Topics MCQs GPU Architecture and Usage MCQs Quantum Computing Basics MCQs Neuromorphic Computing MCQs Emerging Trends Cloud Computing Architectures MCQs Edge Computing MCQs AI Accelerators MCQs Related Posts:Target code generation(MCQs)1000 Ideas to start a Youtube channel and Blog when your target is AmericaWhich of the following is the first step when defining your target market?Which of the following is the first indigenously developed pilotless target aircraft?Techniques to Overcome Hazards (Stalling, Forwarding, Branch Prediction) MCQsBranch Prediction and Speculation MCQs
