Digital Logic Design Past Papers 

Paper 1:  DLD

Course Title: Digital Logic Design (Theory)

Total Marks: 30

Time allowed: 1 Hour

Instructions:

Clearly mention your name, arid number, and a section on your answer sheet.

Question 01:

Design a combinational circuit that has a 3-bit input and a single output (F) specified as follows:

(6 Points)

F=0, when the input is less than (5)

F= 1, otherwise

Question 02:

Construct a 3-bit asynchronous up counter by using a JK flip-flop. Draw its timing diagram and also count table.

(6 Points)

Question 03: Draw and explain the working of the 3-bit universal shift register.

(6 Points)

Question 04: Draw truth table and circuit diagram 16 x 1 multiplexer using 4 x 1.

(6 Points)

Question 05:

(6 Points) Design a four-bit shift register with parallel load using D flip-flops. There are two control inputs: shift and load When shift-1, the content of the register is shifted by one position. New data are transferred into the register when load-1 and shift-0. If both control inputs are equal to 0, the content of the register does not change.

 

Paper 2:  DLD

Course Title: Digital Logic Design (Practical)

Time allowed: 20 Minutes

Total Marks: 20

Instructions:

Only write your name or arid number on your question paper.

Clearly mention Degree Program (BSCSjBSIT) and Semester (2) on your answer sheet.

(5 Points)

Question 01:

A five bit bidirectional shift register has initial content 10101. The register shifted four times to the left with the serial input being 01010 and shifted six times to the right with the serial input being 0011100. What are the contents of the register at the end?

(5 Points)

Question 02:

Design 8 to 3 encoder. Also draw its diagram and truth table

(5 Points)

Question 03:

Draw a diagram so that data is loaded parallel and then it is shifted from left to right instead of night to left. Be sure to mention where the data enters this register and where the data exits

(5 Points)

Question 04:

Construct a JK flip-flop using SR flip-flop. Also draw its truth table and explain its working.

 

[OBJECTIVE]

Subject: Digital Logic Design

Time Allowed: 15 Minutes

Max Marks: 10

NOTE: Attempt this Paper on this Question Sheet only. Please encircle the correct option. Division of marks is given in front of each question. This Paper will be collected back after expiry of time limit mentioned above.

 

Part-I  Answer the following Questions, cutting and overwriting are not allowed. (10)

  1. According to boolean algebra absorption law, which of following is correct?
  2. x+xy=x B. (aty)=xy
  3. xyty=x D. x+y=y
  4. A binary variable can take values
  5. 0 only B. 0 and -1
  6. 0 and 1 D. 1 and 2
  7. Circuits that employs memory elements in addition to gates is called
  8. combinational circuit B. sequential circuit
  9. combinational sequence D. series
  10. Full subtract circuits have
  11. 3 inputs and 2 outputs B. 1 input and | output
  12. both a and b D. None
  13. A circuit that converts n inputs to 2*n outputs is called
  14. encoder B. decoder
  15. comparator D, carry look ahead
  16. Decoder is a
  17. combinational circuit B. sequential circuit
  18. complex circuit D. gate
  19. One that is not outcome of magnitude comparator is
  20. a>b B. a-b
  21. a<h D. a=b
  22. 3×8 decoder will have
  23. 3 inputs B. 4 inputs
  24. 5 inputs D. 6 inputs
  25. 4 to 1 mux would have
  26. 2 inputs B. 3 inputs
  27. 4 inputs D. 5 inputs
  28. To design a 4 x 16 Decoder how many 2 x 4 decoder are needed?
  29. 4 B. 2
  30. 3 D. 4

 

[SUBJECTIVE]

Subject: Digital Logic Design

Time Allowed: 2 Hours 45 Minutes

Max Marks: 50

NOTE: ATTEMPT THIS (SUBJECTIVE) ON SEPARATE ANSWER SHEET PROVIDED

 

Part-II  Give Short Answers, Each question carries equal marks. (20)

Q#1: Convert 2455.30 from Decimal to Octal number system.

Q#2: Perform M-N using r-1’s complement where M=1 100 and N=1001 are in binary number system.

Q#3: Perform the BCD addition on 259 + 378

Q#4: Draw the truth table for the following. F (A, B, C) = (A’+B’) (A’+B’+C’) (B +C)

Q#5: To implement F(A,B,C,D) = & (0,1,2,4,8,9,15) using multiplexer with three variables A, B and C as select lines, What size of MUX is required? What size of decoder is required to implement the same function?

 

 

Part-II  Give Short Answers, Each question carries equal marks. (20)

Q#1: Simplify the following function using K-Map in POS form.

F=B’D+B’C+ABCD

d=A’BD+AB’C’D’

Q#2: Implement the following function using multiplexer. Keep three variables A, B and D as select lines to the multiplexer.

F(A,B,C,D) = zr (0,1.2,4,8,9,35)

Q#3. Draw the logic circuit diagram for 2-bit register using D flip flops capable of performing the following operations:

Control Inputs                                                   Operation

X1X8

0              0                                                              Shift Left

0              1                                                              Shift Right

1              0                                                              Complement

1              1                                                              Parallel Load

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