ASIC Design and FPGAs MCQs Quizlet (Bank of Solved Questions Answers)
By: Prof. Dr. Fazal Rehman | Last updated: March 3, 2022
ASIC Design and FPGAs MCQs Quizlet (Bank of Solved Questions Answers)
1. What is the inputs in the PLD is given through_______A. OR gatesB. NAND gatesC. AND gatesD. NOR gates
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B
2. PAL stands for…A. Programmable Array LogicB. Programmable Logic ArrayC. Programmable Array LoadedD. None of the these
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A
3. What are the Outputs of AND gate in PLD is said to be _____A. Both input and output sameB. Strobe linesC. Output linesD. Input linesE. None of the these
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C
4. Which type of PLD should be used, for programmable logic functions?A. PALB. SLDC. PLAD. CPLD
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D
5. FPGA device are __________ type.A. PLDB. EPROMC. SROMD. SLD
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A
6. FPGA stands for…A. Field Program Gate ArrayB. First Program Gate ArrayC. Field Programmable Gate ArrayD First programmable Gate Array
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C
7. Which of the following full form of VLSI?A. Very Long Single IntegrationB. Very Large Scale IntegrationC. Very Least Scale IntegrationD. None of the these
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B
8. Vertical and horizontal directions in FPGA are separated by_______A. A channelB. A lineC. A flip-flopD. A strobe
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A
9. Which of the following are applications of PLAs?A. Configurable PALsB. Registered PALsC. FPGA programsD. All of the theseE. Both A & B
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E
10. The following logic families have the shortest propagation delay…A. AS-TTLB. S-TTLC. HCMOSD. HS-TTL
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A
11. What is the maximum noise voltage that may appear at the input of a logic gate without changing the logical state of its output is termed as _______A. Noise ImmunityB. Noise MarginC. White NoiseD. None of the these
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B
12. What is the Propagation delay?A. the time taken for the output of a gate to change after the intermediates have changedB. the time taken for the input of a gate to change after the intermediates have changedC. the time taken for the input of a gate to change after the outputs have changedD. the time taken for the output of a gate to change after the inputs have changed
