FPGA and ASIC Implementation — MCQs – EE

1. What does FPGA stand for?
(A) Field Programmable Gate Array
(B) Fast Programmable Gate Application
(C) Field Processing General Array
(D) Flexible Programmable Gate Architecture

2. What does ASIC stand for?
(A) Application-Specific Integrated Circuit
(B) Advanced System Integrated Chip
(C) Analog Signal Integrated Circuit
(D) Automatic Switching Integrated Chip

3. FPGAs are mainly used for:
(A) Prototyping and reconfigurable designs
(B) Mass production
(C) Analog signal processing
(D) Memory storage only

4. ASICs are mainly used for:
(A) High-volume production with fixed functionality
(B) Reconfigurable designs
(C) Temporary implementations
(D) Laboratory testing

5. The main advantage of FPGA is:
(A) Reconfigurability after manufacturing
(B) High unit cost for large volumes
(C) Long design time
(D) Fixed logic structure

6. The main advantage of ASIC is:
(A) Optimized performance and low power for specific tasks
(B) Reconfigurable logic
(C) Higher flexibility
(D) Easy to modify after fabrication

7. FPGA configuration is done using:
(A) Programmable logic blocks and interconnects
(B) Fixed hardware connections
(C) Analog circuits
(D) Magnetic memory cells

8. The basic programmable element in an FPGA is called a:
(A) Logic Block
(B) Flip-flop
(C) Decoder
(D) Counter

9. The interconnection in FPGA is managed by:
(A) Programmable routing resources
(B) Fixed metal layers
(C) Hard-wired gates
(D) Analog paths

10. The configuration data for an FPGA is stored in:
(A) SRAM or Flash memory
(B) ROM only
(C) EPROM only
(D) Hard disk

11. In an FPGA, the I/O blocks are used for:
(A) Interfacing external signals with internal logic
(B) Arithmetic operations
(C) Memory storage
(D) Clock generation

12. Which of the following is an example of FPGA manufacturer?
(A) Xilinx
(B) Intel
(C) AMD
(D) Texas Instruments

13. Which company manufactures ASICs?
(A) TSMC
(B) Xilinx
(C) Altera
(D) Lattice

14. The design flow of FPGA begins with:
(A) HDL coding and synthesis
(B) Fabrication
(C) Packaging
(D) Mask creation

15. The main hardware description languages used for FPGA design are:
(A) VHDL and Verilog
(B) C and C++
(C) Python and Java
(D) MATLAB and Simulink

16. In FPGA, the configuration is loaded:
(A) At power-up or on demand
(B) Permanently during manufacturing
(C) Only once
(D) By soldering connections

17. ASIC design requires the creation of:
(A) Photomasks for fabrication
(B) HDL source only
(C) Programmable bitstreams
(D) Field configurations

18. Which type of ASIC is partially customizable?
(A) Semi-custom ASIC
(B) Full-custom ASIC
(C) Standard-cell ASIC
(D) Gate array ASIC

19. Which of the following is NOT an advantage of FPGA?
(A) Fixed power efficiency for all designs
(B) Fast prototyping
(C) Field reprogrammability
(D) Shorter development time

20. The design time for ASIC compared to FPGA is:
(A) Much longer
(B) Shorter
(C) Equal
(D) Negligible

21. The per-unit cost of ASICs is:
(A) Low for high-volume production
(B) High for high-volume production
(C) Constant for all volumes
(D) Higher than FPGA always

22. FPGA is suitable for:
(A) Rapid prototyping and testing
(B) Permanent consumer products only
(C) Long production cycles
(D) Analog designs

23. In FPGA architecture, CLB stands for:
(A) Configurable Logic Block
(B) Circuit Logic Base
(C) Central Logic Buffer
(D) Conditional Logic Branch

24. The logic blocks in FPGAs contain:
(A) Look-Up Tables (LUTs) and Flip-Flops
(B) Transistors and capacitors
(C) Diodes and resistors
(D) Adders and counters only

25. A hard-core in an FPGA refers to:
(A) Fixed function blocks like processors
(B) Reconfigurable logic
(C) External memory
(D) Temporary routing

26. A soft-core processor in FPGA is:
(A) Implemented using programmable logic
(B) Fabricated permanently
(C) Stored in ROM
(D) Not modifiable

27. The synthesis process converts HDL code into:
(A) Gate-level netlist
(B) Machine code
(C) Testbench code
(D) Layout diagram

28. Place and Route tools in FPGA design are used for:
(A) Mapping logic onto physical hardware
(B) Writing HDL code
(C) Simulating functionality
(D) Generating timing diagrams

29. Bitstream generation in FPGA design occurs:
(A) After synthesis and implementation
(B) Before HDL simulation
(C) Before logic synthesis
(D) During fabrication

30. The main disadvantage of ASICs compared to FPGAs is:
(A) Lack of reconfigurability after fabrication
(B) Lower performance
(C) Smaller integration density
(D) Higher power consumption