CMOS Inverter and Logic Gates — MCQs – EE

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1. The term CMOS stands for:



2. A CMOS inverter consists of:



3. In a CMOS inverter, when the input is low, the output is:



4. In a CMOS inverter, when the input is high, the output is:



5. The PMOS transistor in a CMOS inverter conducts when the input is:



6. The NMOS transistor in a CMOS inverter conducts when the input is:



7. The main advantage of CMOS logic is:



8. The output of a CMOS inverter is ideally:



9. The switching point of a CMOS inverter depends on:



10. The voltage transfer characteristic (VTC) of a CMOS inverter has:



11. The static power consumption in CMOS occurs primarily due to:



12. Dynamic power dissipation in CMOS circuits is mainly due to:



13. The propagation delay in CMOS inverter increases with:



14. The noise margin of a CMOS inverter is:



15. CMOS logic gates are preferred because they offer:



16. The basic logic gates built using CMOS are:



17. A CMOS NAND gate conducts to logic low output when:



18. A CMOS NOR gate conducts to logic high output when:



19. In a CMOS NAND gate, the NMOS transistors are connected in:



20. In a CMOS NOR gate, the PMOS transistors are connected in:



21. In CMOS logic, fan-out refers to:



22. The main limitation of CMOS technology is:



23. The complementary operation of CMOS means:



24. A logic ‘1’ at the output of a CMOS inverter corresponds to:



25. A logic ‘0’ at the output of a CMOS inverter corresponds to:



26. The short-circuit current in CMOS occurs during:



27. The complementary action in CMOS gates ensures:



28. A CMOS inverter provides the basic building block for:



29. The output impedance of a CMOS inverter in steady states is:



30. The switching threshold of a CMOS inverter ideally lies:



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