1. The term CMOS stands for:
(A) Complementary Metal Oxide Semiconductor
(B) Combined Metal Oxide Semiconductor
(C) Controlled Metal Oxide Semiconductor
(D) Composite Metal Oxide Semiconductor
2. A CMOS inverter consists of:
(A) One NMOS and one PMOS transistor
(B) Two NMOS transistors
(C) Two PMOS transistors
(D) One BJT and one MOSFET
3. In a CMOS inverter, when the input is low, the output is:
(A) High
(B) Low
(C) Floating
(D) Undefined
4. In a CMOS inverter, when the input is high, the output is:
(A) Low
(B) High
(C) Zero current
(D) Same as input
5. The PMOS transistor in a CMOS inverter conducts when the input is:
(A) Low
(B) High
(C) Floating
(D) Undefined
6. The NMOS transistor in a CMOS inverter conducts when the input is:
(A) High
(B) Low
(C) Zero
(D) Floating
7. The main advantage of CMOS logic is:
(A) Very low static power dissipation
(B) High static power dissipation
(C) High noise generation
(D) Low switching speed
8. The output of a CMOS inverter is ideally:
(A) The complement of the input
(B) Equal to the input
(C) Always zero
(D) Always one
9. The switching point of a CMOS inverter depends on:
(A) The ratio of NMOS and PMOS sizes
(B) Supply voltage only
(C) Frequency of operation
(D) Load capacitance only
10. The voltage transfer characteristic (VTC) of a CMOS inverter has:
(A) A sharp transition region
(B) A linear response
(C) A constant output
(D) Multiple peaks
11. The static power consumption in CMOS occurs primarily due to:
(A) Leakage currents
(B) Short-circuit current
(C) Resistive heating
(D) Switching loss
12. Dynamic power dissipation in CMOS circuits is mainly due to:
(A) Charging and discharging of load capacitances
(B) Reverse leakage current
(C) Forward conduction loss
(D) Breakdown voltage
13. The propagation delay in CMOS inverter increases with:
(A) Load capacitance
(B) Supply voltage
(C) Channel mobility
(D) Shorter channel length
14. The noise margin of a CMOS inverter is:
(A) High
(B) Low
(C) Zero
(D) Undefined
15. CMOS logic gates are preferred because they offer:
(A) High noise immunity and low power
(B) Low noise and high power
(C) Low switching speed
(D) High static current
16. The basic logic gates built using CMOS are:
(A) NOT, NAND, NOR
(B) AND, OR only
(C) XOR, XNOR only
(D) Flip-flops only
17. A CMOS NAND gate conducts to logic low output when:
(A) All inputs are high
(B) All inputs are low
(C) One input is low
(D) Both inputs are floating
18. A CMOS NOR gate conducts to logic high output when:
(A) All inputs are low
(B) Any input is high
(C) One input is floating
(D) All inputs are high
19. In a CMOS NAND gate, the NMOS transistors are connected in:
(A) Series
(B) Parallel
(C) Cross-coupled
(D) Cascaded
20. In a CMOS NOR gate, the PMOS transistors are connected in:
(A) Series
(B) Parallel
(C) Cascaded
(D) Differential pair
21. In CMOS logic, fan-out refers to:
(A) The number of inputs driven by a single output
(B) The output voltage level
(C) The number of transistors
(D) The gate capacitance
22. The main limitation of CMOS technology is:
(A) Sensitivity to static discharge
(B) High static power
(C) Low integration density
(D) Poor speed performance
23. The complementary operation of CMOS means:
(A) PMOS and NMOS are never ON simultaneously
(B) PMOS and NMOS always ON together
(C) Only PMOS conducts
(D) Both transistors always OFF
24. A logic ‘1’ at the output of a CMOS inverter corresponds to:
(A) Supply voltage (VDD)
(B) Ground
(C) Half of VDD
(D) Floating potential
25. A logic ‘0’ at the output of a CMOS inverter corresponds to:
(A) Ground (0V)
(B) Supply voltage (VDD)
(C) Half of VDD
(D) Undefined voltage
26. The short-circuit current in CMOS occurs during:
(A) Switching transition
(B) Static operation
(C) Power-down mode
(D) Idle state
27. The complementary action in CMOS gates ensures:
(A) Very low static current
(B) High static current
(C) High input capacitance
(D) Constant current operation
28. A CMOS inverter provides the basic building block for:
(A) All CMOS logic gates
(B) Only flip-flops
(C) Only amplifiers
(D) Power circuits
29. The output impedance of a CMOS inverter in steady states is:
(A) Very low
(B) Very high
(C) Moderate
(D) Infinite
30. The switching threshold of a CMOS inverter ideally lies:
(A) Near half of the supply voltage
(B) At zero volts
(C) Near the supply voltage
(D) Undefined