1. : What is an SR Latch primarily used for in digital circuits?
(A) To store a single bit of data temporarily
(B) To perform arithmetic operations
(C) To generate clock signals
(D) To convert analog signals to digital
2. : What are the two inputs of an SR Latch?
(A) Reset and Hold
(B) Set and Reset
(C) Clock and Enable
(D) Data and Clock
3. : What is the output of an SR Latch if both Set (S) and Reset (R) inputs are LOW (0)?
(A) Output HIGH (1)
(B) Output LOW (0)
(C) Output depends on gate configuration
(D) Output cannot be determined
4. : What happens if both Set (S) and Reset (R) inputs of an SR Latch are HIGH (1)?
(A) Invalid state, output unpredictable
(B) Output remains unchanged
(C) Output becomes LOW (0)
(D) Output becomes HIGH (1)
5. : Which gate configuration is used to implement an SR Latch?
(A) Two cross-coupled NAND gates
(B) Two cross-coupled NOR gates
(C) One AND gate and one OR gate
(D) One XOR gate and one NOT gate
6. : What is the primary purpose of a D Latch in digital circuits?
(A) To store a single bit of data temporarily
(B) To perform arithmetic operations
(C) To generate clock signals
(D) To convert analog signals to digital
7. : What are the two inputs of a D Latch?
(A) Data and Enable
(B) Set and Reset
(C) Clock and Data
(D) Data and Clock
8. : What is the output of a D Latch if the Data input is LOW (0) and the Enable input is HIGH (1)?
(A) Output HIGH (1)
(B) Output LOW (0)
(C) Output depends on gate configuration
(D) Output cannot be determined
9. : What is the output of a D Latch if the Data input is HIGH (1) and the Enable input is LOW (0)?
(A) Output HIGH (1)
(B) Output LOW (0)
(C) Output depends on gate configuration
(D) Output cannot be determined
10. : Which gate configuration is used to implement a D Latch?
(A) Two cross-coupled NAND gates
(B) Two cross-coupled NOR gates
(C) One AND gate and one OR gate
(D) One XOR gate and one NOT gate
11. : In an SR Latch, what is the state when both Set (S) and Reset (R) inputs are LOW (0)?
(A) Set
(B) Reset
(C) Invalid state
(D) Hold
12. : In an SR Latch, what is the state when Set (S) input is HIGH (1) and Reset (R) input is LOW (0)?
(A) Set
(B) Reset
(C) Invalid state
(D) Hold
13. : In an SR Latch, what is the state when Set (S) input is LOW (0) and Reset (R) input is HIGH (1)?
(A) Set
(B) Reset
(C) Invalid state
(D) Hold
14. : In an SR Latch, what is the state when both Set (S) and Reset (R) inputs are HIGH (1)?
(A) Set
(B) Reset
(C) Invalid state
(D) Hold
15. : In a D Latch, what is the state when the Data input is LOW (0) and the Enable input is HIGH (1)?
(A) Set
(B) Reset
(C) Invalid state
(D) Hold
16. : In a D Latch, what is the state when the Data input is HIGH (1) and the Enable input is LOW (0)?
(A) Set
(B) Reset
(C) Invalid state
(D) Hold
17. : What is the output of an SR Latch with S=1, R=0 initially, and then S=0, R=0?
(A) Q = 0, Q’ = 1
(B) Q = 1, Q’ = 0
(C) Q = 0, Q’ = 0
(D) Q = 1, Q’ = 1
18. : What is the output of an SR Latch with S=0, R=1 initially, and then S=0, R=0?
(A) Q = 0, Q’ = 1
(B) Q = 1, Q’ = 0
(C) Q = 0, Q’ = 0
(D) Q = 1, Q’ = 1
19. : What is the output of a D Latch with D=1 initially, and then D=0?
(A) Q = 0, Q’ = 1
(B) Q = 1, Q’ = 0
(C) Q = 0, Q’ = 0
(D) Q = 1, Q’ = 1
20. : What is the output of a D Latch with D=0 initially, and then D=1?
(A) Q = 0, Q’ = 1
(B) Q = 1, Q’ = 0
(C) Q = 0, Q’ = 0
(D) Q = 1, Q’ = 1
