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Important MCQs of DLD

1. : Why do we use a demultiplexer?

(A) Route the data from a single input to one of many outputs


(B) Select data from several inputs and route it to a single output


(C) Perform serial to parallel conversion


(D) Both A and B



2. : Which is an example of synchronous inputs?

(A) Preset input (PRE)


(B) EN input


(C) J-K input


(D) Clear Input (CLR)



3. : Which one is the second step of making a transition table?

(A) Determining feedback loop


(B) Designating output of loops


(C) Deriving functions of Y


(D) Plotting



4. : An OR gate can be imagined to look like ____________

(A) Switches connected in parallel


(B) Switches connected in series


(C) MOS transistors connected in series


(D) None of these



5. : The change from a current state to the next state is determined by

(A) Previous state and outputs


(B) Current state and outputs


(C) Current state and the inputs


(D) Previous state and inputs



6. : Each gate takes time for delay of

(A) 2 to 10 ns


(B) 3 to 10 ns


(C) 1 to 5 ns


(D) 3 to 5 ns



7. : In which combination of gates is an arbitrary Boolean function not possible?

(A) OR gates and exclusive OR gate only


(B) NAND gates only


(C) OR gates and NOT gates only


(D) OR gates and AND gates only



8. : Which one of the following is used to simplify the circuit that determines the next state?

(A) State diagram


(B) State assignment


(C) State reduction


(D) Next state table



9. : When both inputs are ____________, the NAND latch works.

(A) Inverted


(B) 0


(C) 1


(D) Don’t cares



10. : ____________ adders are needed to construct an m-bit parallel adder.

(A) m+1


(B) m-1


(C) m


(D) m/2



11. : ________________ is converted by a multiplexer with a register circuit.

(A) Serial data to serial


(B) Serial data to parallel


(C) Parallel data to serial


(D) Parallel data to parallel



12. : Changing input in more than one state is called _______________

(A) Undefined condition


(B) Ideal condition


(C) Reset condition


(D) Race condition



13. : Select the function of a multiplexer.

(A) To perform serial to parallel conversion


(B) To decode information


(C) To transmit data on N lines


(D) To select 1 out of N input data sources and transmit it to a single channel



14. : Select the combinational logic circuit which produces a specific binary word or number.

(A) Encoder


(B) Multiplexer


(C) Decoder


(D) Demultiplexer



15. : Which circuit can be used as a parallel to serial converter?

(A) Decoder


(B) Demultiplexer


(C) Multiplexer


(D) Digital counter



16. : What is the function of shift registers?

(A) Shifting


(B) Rotating


(C) Both A and B


(D) Adding



17. : The 7-segment display produces output

(A) a to g


(B) a to f


(C) a to b


(D) a to z



18. : What is used for BCD to 7-segment conversion?

(A) Multiplexer


(B) Encoder


(C) Decoder


(D) Demultiplexer



19. : Select the universal gate.

(A) NAND


(B) AND


(C) OR


(D) NOT



20. : Which one is NOT an operation provided by a magnitude comparator?

(A) Equal


(B) Addition


(C) Greater


(D) Less



21. : The enable input of the shift register is commonly called?

(A) Load


(B) Strobe


(C) Reset


(D) Store



 

MCQs of Digital Logic Design (DLD)

Introduction to Digital Systems

  1. Analog vs. Digital signals MCQs
  2. Binary numbers and arithmetic MCQs
  3. Logic levels and noise margins MCQs

Boolean Algebra

  1. Basic logic operations (AND, OR, NOT) MCQ
  2. Laws and theorems of Boolean algebra MCQ
  3. De Morgan’s Theorems MCQ
  4. Canonical forms (Sum of Products, Product of Sums) MCQ
  5. Simplification techniques (Karnaugh Maps, Quine-McCluskey method) MCQ

Combinational Logic

Logic Gates

  1. Basic gates (AND, OR, NOT) Gat MCQ
  2. Universal gates (NAND, NOR) Gat MCQs
  3. XOR and XNOR gates MCQ

Combinational Circuits

  1. Design and analysis of combinational circuits MCQ
  2. Multiplexers and Demultiplexers MCQ
  3. Encoders and Decoders MCQ
  4. Binary Adders (Half adder, Full adder) MCQ
  5. Subtractors and Arithmetic Logic Units (ALU) MCQ
  6. Comparators MCQ in DLD

Sequential Logic

Flip-Flops and Latches

  1. SR Latch, D Latch MCQ
  2. Flip-Flops (SR, D, JK, T) MCQ
  3. Characteristic equations and excitation tables MCQ
  4. Edge-triggered vs. level-triggered devices MCQ

Counters and Registers

  1. Synchronous, Asynchronous (ripple), Up/Down counters MCQs
  2. Shift registers (SIPO, PISO, SISO, PIPO) MCQs

State Machines

Finite State Machines (FSMs)

  1. Moore and Mealy machines MCQs

Memory and Programmable Logic MCQs

Memory Devices

  1. Read-Only Memory (ROM)
  2. Random Access Memory (RAM)
  3. Programmable Logic Devices (PLDs) MCQs
  4. Field Programmable Gate Arrays (FPGAs) MCQs

More MCQs of Digital Logic Design (DLD)

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