1. : Which level of cache is typically the closest to the CPU core?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
2. : What is the primary function of L1 Cache?
(A) To store frequently accessed instructions and data for quick access by the CPU
(B) To increase the overall system memory size
(C) To manage virtual memory
(D) To handle disk I/O operations
3. : Which level of cache usually has the largest size among L1, L2, and L3?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Registers
4. : What is a key characteristic of L1 Cache compared to L2 and L3 Caches?
(A) L1 Cache is faster but smaller
(B) L1 Cache is slower but larger
(C) L1 Cache is typically located off-chip
(D) L1 Cache has the highest latency
5. : Which cache level is designed to reduce the performance gap between the CPU and main memory?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
6. : What is the typical size range for L2 Cache?
(A) 8 KB to 64 KB
(B) 256 KB to 1 MB
(C) 2 MB to 8 MB
(D) 16 MB to 32 MB
7. : Which cache level has the lowest latency but also the smallest capacity?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
8. : What is the typical size range for L3 Cache?
(A) 16 KB to 128 KB
(B) 128 KB to 512 KB
(C) 1 MB to 16 MB
(D) 32 MB to 64 MB
9. : Which level of cache usually implements the “write-back” policy?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
10. : What is the main advantage of L3 Cache over L1 and L2 Caches?
(A) L3 Cache has higher capacity
(B) L3 Cache has lower latency
(C) L3 Cache is faster
(D) L3 Cache is closer to the CPU
11. : What is a common cache replacement policy for L1 Cache?
(A) Least Recently Used (LRU)
(B) First-In-First-Out (FIFO)
(C) Random Replacement
(D) Write-through
12. : Which cache level typically uses the “write-through” policy?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
13. : What is the primary role of L2 Cache in a multi-core processor system?
(A) To serve as an intermediate cache between L1 and L3 Caches
(B) To store all data permanently
(C) To handle network data
(D) To manage virtual memory
14. : What is a key characteristic of L3 Cache in terms of its location?
(A) L3 Cache is shared among multiple CPU cores
(B) L3 Cache is dedicated to a single CPU core
(C) L3 Cache is located off-chip
(D) L3 Cache has the smallest capacity
15. : Which cache level typically has the highest bandwidth?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
16. : What is the effect of increasing L2 Cache size on overall system performance?
(A) It can reduce cache miss rates and improve performance
(B) It increases cache latency
(C) It decreases the system’s bandwidth
(D) It has no impact on performance
17. : Which of the following caches is usually located on the CPU chip itself?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) All of the above
18. : What is the typical access time for L3 Cache compared to L1 Cache?
(A) L3 Cache access time is faster
(B) L3 Cache access time is the same
(C) L3 Cache access time is slower
(D) L3 Cache access time varies
19. : Which cache level typically implements the largest cache line size?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
20. : What is a common replacement policy for L3 Cache?
(A) Least Recently Used (LRU)
(B) First-In-First-Out (FIFO)
(C) Random Replacement
(D) Write-through
21. : What is the impact of cache associativity on cache performance?
(A) Higher associativity reduces cache misses but increases access time
(B) Higher associativity increases cache misses but reduces access time
(C) Lower associativity increases cache hits but decreases performance
(D) Lower associativity has no impact on performance
22. : Which of the following is true about cache coherence in multi-core systems?
(A) Cache coherence ensures that all cores see the same data for a given memory address
(B) Cache coherence is only relevant for L1 Cache
(C) Cache coherence is not necessary for L2 Cache
(D) Cache coherence ensures that only L3 Cache data is synchronized
23. : What is the function of cache line eviction in L1 Cache?
(A) To remove old or less frequently used data to make space for new data
(B) To increase cache size
(C) To manage disk storage
(D) To update the main memory
24. : Which cache level usually has the lowest power consumption per bit?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
25. : How does increasing the cache size affect cache miss rate?
(A) It typically reduces the cache miss rate
(B) It increases the cache miss rate
(C) It has no effect on the cache miss rate
(D) It depends on the replacement policy
26. : What is the common method used to increase cache hit rates?
(A) Increasing cache size
(B) Reducing cache associativity
(C) Decreasing cache line size
(D) Increasing main memory size
27. : What type of cache is shared among multiple cores in a multi-core processor?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) All of the above
28. : What is the primary purpose of a “write-back” policy in L2 Cache?
(A) To update the main memory only when data is evicted from the cache
(B) To write data to both the cache and main memory immediately
(C) To bypass the cache for write operations
(D) To increase cache access speed
29. : Which cache level typically has the largest latency but also the largest capacity?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
30. : What is the typical cache access time for L1 Cache compared to L3 Cache?
(A) L1 Cache access time is faster
(B) L1 Cache access time is slower
(C) L1 Cache access time is the same
(D) L1 Cache access time is variable
31. : What is a characteristic of “set-associative” cache mapping?
(A) It maps blocks of data to a specific set of cache lines
(B) It maps blocks of data to any cache line
(C) It maps each block to a single cache line
(D) It has no specific mapping
32. : What cache level is typically used to store data for multiple cores to access simultaneously?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
33. : Which level of cache is most likely to use the “Least Recently Used” (LRU) replacement policy?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
34. : What does the “write-through” policy ensure in L1 Cache?
(A) Data written to the cache is also written to the main memory immediately
(B) Data is written to the cache and updated later in the main memory
(C) Data is bypassed from the cache and written directly to the main memory
(D) Data is only written to the cache and not the main memory
35. : Which cache level is usually the most effective at reducing latency for frequently accessed data?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
36. : What is the typical impact of “cache associativity” on cache performance?
(A) Higher associativity reduces cache misses but may increase latency
(B) Higher associativity increases cache misses but decreases latency
(C) Lower associativity reduces performance but increases capacity
(D) Associativity has no impact on performance
37. : Which cache level is typically the first to handle cache requests?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
38. : What is the impact of a “write-around” policy on cache performance?
(A) It bypasses the cache for write operations and directly writes to the main memory
(B) It updates both cache and main memory simultaneously
(C) It increases cache hit rate by writing to the cache first
(D) It reduces cache size
39. : What is the common role of L3 Cache in modern processors?
(A) To serve as a large, shared cache among multiple cores
(B) To act as the first level of cache accessed by the CPU
(C) To replace L1 Cache
(D) To manage I/O operations
40. : Which cache level typically has the lowest cost per bit?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
41. : What does “cache coherence” mean in a multi-core system?
(A) Ensuring all caches in the system have consistent data
(B) Synchronizing the cache with the main memory
(C) Increasing the size of the cache
(D) Decreasing the access time of the cache
42. : How does a larger L2 Cache affect system performance?
(A) It can reduce the frequency of L1 Cache misses and improve overall performance
(B) It increases L1 Cache latency
(C) It has no impact on performance
(D) It decreases the system’s overall memory bandwidth
43. : Which cache level is generally not shared among multiple cores?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
44. : What is the typical function of “cache write policies” in CPU caches?
(A) To determine how data writes are managed between the cache and main memory
(B) To manage the size of the cache
(C) To increase cache access speed
(D) To handle disk storage
45. : Which level of cache typically implements the “write-back” policy to reduce memory traffic?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
46. : What is the effect of increasing the cache line size on cache performance?
(A) It can improve cache performance by reducing the number of cache misses
(B) It decreases cache hit rate
(C) It increases latency for cache accesses
(D) It has no effect on performance
47. : What is the main benefit of a “write-back” cache policy in terms of cache performance?
(A) It reduces the number of write operations to main memory
(B) It increases the write latency
(C) It writes data to main memory immediately
(D) It has no impact on performance
48. : Which cache level usually implements the largest “write-back” cache policy?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory
49. : What is a typical characteristic of “write-through” cache policy?
(A) Writes data to both the cache and main memory simultaneously
(B) Updates data only in the cache
(C) Delays writing data to main memory until the cache line is evicted
(D) Reduces cache size
50. : Which cache level is usually the last level of cache accessed before main memory?
(A) L1 Cache
(B) L2 Cache
(C) L3 Cache
(D) Main Memory