# Past Guess Paper of Digital Logic Design DLD

Past Guess Paper of Digital Logic Design (DLD).

## Guess Paper 1 : Digital Logic Design (DLD)

University Name – Confidential

NOTE: Q.1 is compulsory, attempt any four questions from the remaining. All questions carry equal marks. Phones and other Electronic Gadgets are not allowed.

Paper : Digital Logic Design (DLD)

Time Allowed: 3 hours

Examination:   Final, Fall – 2020

Total Marks:    70, Passing Marks (35)

Q1:     Convert the following decimal numbers in to binary and then hexadecimal;

• 326
• 16
• 354
• 32

Q2:    Show the following operations using 2s complement:

1.  i) 1110111 – 1011011
2. ii) 1011001 – 10000111

iii) 001001 – 000101

1. iv) 0.0101 – 0.1001

Q3:     What are logic gates? Give the symbol, function and truth table for each of the three Fundamental logic gates.

Q4.      a) Design a 4-bit binary synchronous counter with D flip-flops,

1. b) Design a 4-bit register with the parallel load using RS flip-flops.

Q5:     Construct a state equation for a JK-flip flop with both inputs equal to one.

Q6:    Simplify the following Boolean functions, using 4-variable maps:

1. a) w’z + xz + x’y + wx’z
2. b) wxy + yz + xy’z + x’y

Q7:      Explain shift register and Counter with help of a diagram.

Q8       Write short notes on any two of the following:

1. D master slave flip flop
3. Full subtractor
4. Decoder

## Guess Paper 2 : Digital Logic Design (DLD)

University Name – Confidential

NOTE: Q.1 is compulsory, attempt any four questions from the remaining. All questions carry equal marks. Phones and other Electronic Gadgets are not allowed.

Paper : Digital Logic Design (DLD)

Time Allowed: 3 hours

Examination:   Final, Spring- 2020

Total Marks:    70, Passing Marks (35)

Q.1      Convert decimal 9 into binary, octal and hexadecimal number systems.

Q.2      Draw and explain 4-bit binary Subtractor circuit using Half subtractors.

Q.3      Simplify the following Boolean functions using K-maps.

1. F (A, B, C) = Π (1, 7)
2. F (A, B, C) = Ʃ (1, 2, 3)

Q.4      Implement the following Boolean function with a multiplexer.

F (A, B, C) =(0, 1, 3, 4)

Q.5      implement the following using NAND gate

1. a) AB+CD+AC
2. b) AC+BD

Q.6      a) Perform M-N using 1’s complement

M = 101 N=110

1. b) Perform M-N using 7’s complement

M=161 N = 151

Q.7     Explain the followings.

1. Boolean algebra
2. Truth Table
3. Universal Gates

## Guess Paper 3 : Digital Logic Design (DLD)

University Name – Confidential

NOTE: Q.1 is compulsory, attempt any four questions from the remaining. All questions carry equal marks. Phones and other Electronic Gadgets are not allowed.

Paper : Digital Logic Design (DLD)

Time Allowed: 3 hours

Examination:   Final, Spring- 2019

Total Marks:    70, Passing Marks (35)

Q-1.  Answer the following short questions.                                                                          (14)

1. (10110101.101)2 —————-Convert in decimal
2. 10110112– 01101012———–Subtract the two numbers
3. 11002 × 1002 ——————–Multiply the two binary numbers
4. (1A1)16 ————————–Convert in Binary and Octal
5. 101101111012 ——————Find 1’s & 2’s compliment of given number
7. 011011002 ———————-Convert the binary number into Gray code

Q-2.     A) What is the universal property of NAND or NOr gate? Explain.                                   (5+5+4)

B) Draw the logic circuit for the Boolean expression: C) Apply DeMorgan’s theorem to the following equation:

Q-3.     Differentiate among the following.                                                                            (14)

1. Analog and Digital quantities
2. Multiplexer and Demultiplexer
3. RAM and ROM types of memories
4. Encoding and Decoding
5. Combinational and sequential logic

Q4.      A) Write Boolean expression for the circuit given below.                                             (14) Q- 6.    A) Design and explain the function of Decimal to BCD Encoder.                              (14)

1. B) Briefly explain the construction and working of SR-Flip Flop.

Q- 7.    A) Differentiate between Synchronous and Asynchronous counter.                                        (14)

1. B) Design 3-bit asynchronous counter that counts from binary 000 to 111 states.

Q- 8.    Explain how data bits are entered and shifted through Serial in/Serial Out (SISO) Shift Register. Also draw the diagram of 4-bit Serial in/ Parallel Out (SIPO) shift registers.(14)

## Guess Paper 4 : Digital Logic Design (DLD)

University Name – Confidential

NOTE: Q.1 is compulsory, attempt any four questions from the remaining. All questions carry equal marks. Phones and other Electronic Gadgets are not allowed.

Paper : Digital Logic Design (DLD)

Time Allowed: 3 hours

Examination:   Final, Fall- 2019

Total Marks:    70, Passing Marks (35)

Q.1      Convert the binary number 110101011 into decimal and hexadecimal.

Q.2      Simplify the following Boolean functions using K-maps.

F (A, B, C, D) = Ʃ (0, 1, 5, 8, 9,),

F (A, B, C) =  ∏ (5, 6,7) .

1. 3 Implement 8*1 mux using 2*1 mux.
2. 4 Draw the logic circuit of full adder using truth table.

Q.5      a) Draw the function table of 4-to-2encoder,

1. b) Explain 4-input Multiplexer with the help of circuit Diagram and Function Table.

Q.6      Explain the Operation of magnitude comparator Circuit.

Q.7      Find the 1st and 2nd compliments of the following sequence.

1. a) 11000001110101
2. b) 1101

## Guess Paper 5 : Digital Logic Design (DLD)

University Name – Confidential

NOTE: Q.1 is compulsory, attempt any four questions from the remaining. All questions carry equal marks. Phones and other Electronic Gadgets are not allowed.

Paper : Digital Logic Design (DLD)

Time Allowed: 3 hours

Examination:   Final, Fall- 2018

Total Marks:    70, Passing Marks (35)

Q.1.     Answer the following short questions:                                                                                          (14)

Convert the given Gray code into Binary i.e. 11001101.

Add the given BCD numbers properly. 10000110+00010011.

Draw pulse/timing diagram for the number 110010101100.

Attach even parity bit with the numbers 011011 and 1011101.

Find 1’s and 2’s compliment of the number (10110101)2.

Convert the hexadecimal number (F16.B52)16 in binary number.

Draw the logic circuit for the Boolean expression:

Q.2.     Differentiate among the following. Support your answer with examples and figures (where needed) (14)

1. Analog and Digital quantities.
2. Static RAM and Dynamic RAM.
3. Combinational and sequential logic

Q.3.     Describe the function of the Full-adder circuit with the help of its symbol, truth table,                  logic expression and logic diagram. Also draw only the block diagram of 4-bit parallel binary adder along its logic symbol. (14)

Q.4.     Discuss and compare the operation of SR and JK edge-triggered Flip Flops with the help of circuit diagrams and truth tables. (14)

Q.5.     Describe the function of the 3-Bit Synchronous Binary Counter with the help of its logic diagram and Truth Table. Draw the logic Diagram of 3-bit Up/Down Counter using JK-Flip Flop. (14)

Q.6.     Describe the function of the 4-Bit Serial In/ Serial Out (SISO) shift register with the help of its logic diagram and Truth Table. (14)

Q.7.     Attempt any two of the following: (14)

1. Explain the universal property of NAND gate.
2. Enlist the all steps involved in the design of a synchronous counter.
3. Minimize the given expressions using Karnaugh map.
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